Sai Kiran Cherupally
Orcid: 0000-0002-6305-1935
According to our database1,
Sai Kiran Cherupally
authored at least 9 papers
between 2019 and 2023.
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Bibliography
2023
A 28-nm 8-bit Floating-Point Tensor Core-Based Programmable CNN Training Processor With Dynamic Structured Sparsity.
IEEE J. Solid State Circuits, 2023
2022
IEEE Des. Test, 2022
A 28nm 8-bit Floating-Point Tensor Core based CNN Training Processor with Dynamic Activation/Weight Sparsification.
Proceedings of the 48th IEEE European Solid State Circuits Conference, 2022
Proceedings of the 48th IEEE European Solid State Circuits Conference, 2022
2021
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2021
Leveraging Noise and Aggressive Quantization of In-Memory Computing for Robust DNN Hardware Against Adversarial Input and Weight Attacks.
Proceedings of the 58th ACM/IEEE Design Automation Conference, 2021
2020
ECG Authentication Hardware Design With Low-Power Signal Processing and Neural Network Optimization With Low Precision and Structured Compression.
IEEE Trans. Biomed. Circuits Syst., 2020
A Smart Hardware Security Engine Combining Entropy Sources of ECG, HRV, and SRAM PUF for Authentication and Secret Key Generation.
IEEE J. Solid State Circuits, 2020
2019
ECG Authentication Neural Network Hardware Design with Collective Optimization of Low Precision and Structured Compression.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2019