Sai Charan Vemula

According to our database, Sai Charan Vemula authored at least 2 papers between 2022 and 2023.

Collaborative distances:

• Dijkstra number of six.
• Erdős number of five.

2023

Low area and high throughput implementation of advanced encryption standard hardware accelerator on FPGA using Mux-Demux pair.

N. Renugadevi, Stheya Julakanti, Sai Charan Vemula, Somya Bhatnagar, Shirisha Thangallapally

Secur. Priv., 2023

2022

Methods for improving the implementation of advanced encryption standard hardware accelerator on field programmable gate array-A survey.

N. Renugadevi, Shirisha Thangallapally, Sai Charan Vemula, Stheya Julakanti, Somya Bhatnagar

Secur. Priv., 2022