Sahand Kashani

According to our database, Sahand Kashani authored at least 4 papers between 2022 and 2024.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2024

Performance Interfaces for Hardware Accelerators.

Jiacheng Ma, Rishabh R. Iyer, Sahand Kashani, Mahyar Emami, Thomas Bourgeat, George Candea

Proceedings of the 18th USENIX Symposium on Operating Systems Design and Implementation, 2024

A 475 MHz Manycore FPGA Accelerator for RTL Simulation.

Sahand Kashani, Mahyar Emami, Keisuke Kamahori, Mohammad Sepehr Pourghannad, Ritik Raj, James R. Larus

Proceedings of the 2024 ACM/SIGDA International Symposium on Field Programmable Gate Arrays, 2024

2023

Manticore: Hardware-Accelerated RTL Simulation with Static Bulk-Synchronous Parallelism.

Mahyar Emami, Sahand Kashani, Keisuke Kamahori, Mohammad Sepehr Pourghannad, Ritik Raj, James R. Larus

Proceedings of the 28th ACM International Conference on Architectural Support for Programming Languages and Operating Systems, 2023

2022

Bitfiltrator: A general approach for reverse-engineering Xilinx bitstream formats.

Sahand Kashani, Mahyar Emami, James R. Larus

Proceedings of the 32nd International Conference on Field-Programmable Logic and Applications, 2022