Saghir A. Shaikh

According to our database, Saghir A. Shaikh authored at least 17 papers between 1995 and 2016.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2016

Practices in High-Speed IO testing.

Salem Abdennadher, Saghir A. Shaikh

Proceedings of the 21th IEEE European Test Symposium, 2016

2014

Fast BIST of I/O Pin AC specifications and inter-chip delays.

Stephen Sunter, Saghir A. Shaikh, Qing Lin

Proceedings of the 2014 International Test Conference, 2014

2013

Innovative practices session 3C: Harnessing the challenges of testability and debug of high speed I/Os.

Saghir A. Shaikh

Proceedings of the 31st IEEE VLSI Test Symposium, 2013

2007

Practices in Mixed-Signal and RF IC Testing.

Salem Abdennadher, Saghir A. Shaikh

IEEE Des. Test Comput., 2007

2005

Challenges in High Speed Interface Testing.

Salem Abdennadher, Saghir A. Shaikh

Proceedings of the 14th Asian Test Symposium (ATS 2005), 2005

Practices in Testing of Mixed-Signal and RF SoCs.

Salem Abdennadher, Saghir A. Shaikh

Proceedings of the 14th Asian Test Symposium (ATS 2005), 2005

2004

IEEE Std 1149.6 Implementation for a XAUI-to-Serial 10-Gbps Transceiver.

Saghir A. Shaikh

Proceedings of the Proceedings 2004 International Test Conference (ITC 2004), 2004

2001

Test response compression and bitmap encoding for embedded memories in manufacturing process monitoring.

John T. Chen, Jitendra Khare, Ken Walker, Saghir A. Shaikh, Janusz Rajski, Wojciech Maly

Proceedings of the Proceedings IEEE International Test Conference 2001, Baltimore, MD, USA, 30 October, 2001

2000

Test and Debug of Networking SoCs: A Case Study.

A. Bommireddy, Jitendra Khare, Saghir A. Shaikh, S.-T. Su

Proceedings of the 18th IEEE VLSI Test Symposium (VTS 2000), 30 April, 2000

Manufacturability and Testability Oriented Synthesis.

Saghir A. Shaikh, Jitendra Khare, Hans T. Heineken

Proceedings of the 13th International Conference on VLSI Design (VLSI Design 2000), 2000

Maximizing Wafer Productivity Through Layout Optimization.

Charles H. Ouyang, Hans T. Heineken, Jitendra Khare, Saghir A. Shaikh, Manuel d'Abreu

Proceedings of the 13th International Conference on VLSI Design (VLSI Design 2000), 2000

Wire planning for performance and yield enhancement.

Charles Ouyang, Kyungsuk Ryu, Hans T. Heineken, Jitu Khare, Saghir A. Shaikh, Manuel d'Abreu

Proceedings of the IEEE 2000 Custom Integrated Circuits Conference, 2000

1998

Design of an experience-based assembly sequence planner for mechanical assemblies.

Arun Swaminathan, Saghir A. Shaikh, K. Suzanne Barber

Robotica, 1998

1997

Exploiting Component/Event-Level Parallelism in Concurrent Fault and Design Error Simulation.

Saghir A. Shaikh, Stephen A. Szygenda

Proceedings of the Proceedings 30st Annual Simulation Symposium (SS '97), April 7-9, 1997, 1997

Concurrent Fault and Design Error Simulation in Interactive Simulation Automation System.

Youngmin Hur, Saghir A. Shaikh, Silvian Goldenberg, Dominik Kacprzak, Stephen A. Szygenda

Proceedings of the Proceedings 30st Annual Simulation Symposium (SS '97), April 7-9, 1997, 1997

1996

CON²FERS: A Concurrent Concurrent Fault and Design Error Simulator.

Saghir A. Shaikh, Silvian Goldenberg, Stephen A. Szygenda

Proceedings of the International Conference on Parallel and Distributed Processing Techniques and Applications, 1996

1995

Statistics on concurrent fault and design error simulation.

Brian Grayson, Saghir A. Shaikh, Stephen A. Szygenda

Proceedings of the 1995 International Conference on Computer Design (ICCD '95), 1995