Sagarvarma Sayyaparaju

According to our database1, Sagarvarma Sayyaparaju authored at least 11 papers between 2017 and 2021.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Bibliography

2021
Design of a Robust Memristive Spiking Neuromorphic System with Unsupervised Learning in Hardware.
ACM J. Emerg. Technol. Comput. Syst., 2021

2020
Device-aware Circuit Design for Robust Memristive Neuromorphic Systems with STDP-based Learning.
ACM J. Emerg. Technol. Comput. Syst., 2020

Circuit Techniques for Efficient Implementation of Memristor Based Reservoir Computing.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2020

2019
Fabrication and Performance of Hybrid ReRAM-CMOS Circuit Elements for Dynamic Neural Networks.
Proceedings of the International Conference on Neuromorphic Systems, 2019

A Scan Register Based Access Scheme for Multilevel Non-Volatile Memristor Memory.
Proceedings of the 26th IEEE International Conference on Electronics, Circuits and Systems, 2019

2018
A Twin Memristor Synapse for Spike Timing Dependent Learning in Neuromorphic Systems.
Proceedings of the 31st IEEE International System-on-Chip Conference, 2018

A Mixed-Mode Neuron with On-chip Tunability for Generic Use in Memristive Neuromorphic Systems.
Proceedings of the 2018 IEEE Computer Society Annual Symposium on VLSI, 2018

A bi-memristor synapse with spike-timing-dependent plasticity for on-chip learning in memristive neuromorphic systems.
Proceedings of the 19th International Symposium on Quality Electronic Design, 2018

2017
A mixed-signal approach to memristive neuromorphic system design.
Proceedings of the IEEE 60th International Midwest Symposium on Circuits and Systems, 2017

A practical hafnium-oxide memristor model suitable for circuit design and simulation.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2017

Circuit Techniques for Online Learning of Memristive Synapses in CMOS-Memristor Neuromorphic Systems.
Proceedings of the on Great Lakes Symposium on VLSI 2017, 2017


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