Sagar S. Sabade

According to our database1, Sagar S. Sabade authored at least 14 papers between 2001 and 2006.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Dataset
Other 

Links

On csauthors.net:

Bibliography

2006
Estimation of fault-free leakage current using wafer-level spatial information.
IEEE Trans. Very Large Scale Integr. Syst., 2006

2005
IC Outlier Identification Using Multiple Test Metrics.
IEEE Des. Test Comput., 2005

2004
I<sub>DDX</sub>-based test methods: A survey.
ACM Trans. Design Autom. Electr. Syst., 2004

I<sub>DDQ</sub> data analysis using neighbor current ratios.
J. Syst. Archit., 2004

On Comparison of NCR Effectiveness with a Reduced I{DDQ} Vector Set.
Proceedings of the 22nd IEEE VLSI Test Symposium (VTS 2004), 2004

Comparison of Effectiveness of Current Ratio and Delta-IDDQ Tests.
Proceedings of the 17th International Conference on VLSI Design (VLSI Design 2004), 2004

2003
Use of Multiple IDDQ Test Metrics for Outlier Identification.
Proceedings of the 21st IEEE VLSI Test Symposium (VTS 2003), 27 April, 2003

Immediate Neighbor Difference IDDQ Test (INDIT) for Outlier Identification.
Proceedings of the 16th International Conference on VLSI Design (VLSI Design 2003), 2003

CROWNE: Current Ratio Outliers with Neighbor Estimator.
Proceedings of the 18th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2003), 2003

2002
IDDQ Test: Will It Survive the DSM Challenge?
IEEE Des. Test Comput., 2002

Evaluation of Effectiveness of Median of Absolute Deviations Outlier Rejection-based IDDQ Testing for Burn-in Reduction.
Proceedings of the 20th IEEE VLSI Test Symposium (VTS 2002), Without Testing It's a Gamble, 28 April, 2002

Evaluation of Statistical Outlier Rejection Methods for IDDQ Limit Setting.
Proceedings of the 7th Asia and South Pacific Design Automation Conference (ASP-DAC 2002), 2002

Neighbor Current Ratio (NCR): A New Metric for IDDQ Data Analysis.
Proceedings of the 17th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2002), 2002

2001
Improved wafer-level spatial analysis for I_DDQ limit setting.
Proceedings of the Proceedings IEEE International Test Conference 2001, Baltimore, MD, USA, 30 October, 2001


  Loading...