Sagar Karandikar

Orcid: 0000-0003-3145-776X

According to our database1, Sagar Karandikar authored at least 17 papers between 2013 and 2024.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Links

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Bibliography

2024
FireAxe: Partitioned FPGA-Accelerated Simulation of Large-Scale RTL Designs.
Proceedings of the 51st ACM/IEEE Annual International Symposium on Computer Architecture, 2024

2023
CDPU: Co-designing Compression and Decompression Processing Units for Hyperscale Systems.
Proceedings of the 50th Annual International Symposium on Computer Architecture, 2023

Profiling Hyperscale Big Data Processing.
Proceedings of the 50th Annual International Symposium on Computer Architecture, 2023

2021
Accessible, FPGA Resource-Optimized Simulation of Multiclock Systems in FireSim.
IEEE Micro, 2021

A Hardware Accelerator for Protocol Buffers.
Proceedings of the MICRO '21: 54th Annual IEEE/ACM International Symposium on Microarchitecture, 2021

COBRA: A Framework for Evaluating Compositions of Hardware Branch Predictors.
Proceedings of the IEEE International Symposium on Performance Analysis of Systems and Software, 2021

2020
Chipyard: Integrated Design, Simulation, and Implementation Framework for Custom SoCs.
IEEE Micro, 2020

Invited: Chipyard - An Integrated SoC Research and Implementation Environment.
Proceedings of the 57th ACM/IEEE Design Automation Conference, 2020

FirePerf: FPGA-Accelerated Full-System Hardware/Software Performance Profiling and Co-Design.
Proceedings of the ASPLOS '20: Architectural Support for Programming Languages and Operating Systems, 2020

2019
FireSim: FPGA-Accelerated Cycle-Exact Scale-Out System Simulation in the Public Cloud.
IEEE Micro, 2019

Centrifuge: Evaluating full-system HLS-generated heterogenous-accelerator SoCs using FPGA-Acceleration.
Proceedings of the International Conference on Computer-Aided Design, 2019

FPGA Accelerated INDEL Realignment in the Cloud.
Proceedings of the 25th IEEE International Symposium on High Performance Computer Architecture, 2019

FASED: FPGA-Accelerated Simulation and Evaluation of DRAM.
Proceedings of the 2019 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2019

2018
DESSERT: Debugging RTL Effectively with State Snapshotting for Error Replays across Trillions of Cycles.
Proceedings of the 28th International Conference on Field Programmable Logic and Applications, 2018

2016
Network Requirements for Resource Disaggregation.
Proceedings of the 12th USENIX Symposium on Operating Systems Design and Implementation, 2016

Vector Processors for Energy-Efficient Embedded Systems.
Proceedings of the Fourth ACM International Workshop on Many-core Embedded Systems, 2016

2013
BOSS: Building Operating System Services.
Proceedings of the 10th USENIX Symposium on Networked Systems Design and Implementation, 2013


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