Sagar Dwivedi

According to our database, Sagar Dwivedi authored at least 6 papers between 2017 and 2018.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2018

Logic-based row redundancy technique designed in 7nm FinFET technology for embedded SRAMs.

Vivek Nautiyal, Nishant Nukala, Fakhruddin Ali Bohra, Sagar Dwivedi, Jitendra Dasani, Satinderjit Singh, Gaurav Singla, Martin Kinkade

Proceedings of the 19th International Symposium on Quality Electronic Design, 2018

Self-Timed Shaper Circuit for Wide Memories in Advanced CMOS Technologies.

Vivek Nautiyal, Gaurav Singla, Sagar Dwivedi, Satinderjit Singh, Ingming Chang, Jitendra Dasani, Fakhruddin Ali Bohra

Proceedings of the IEEE International Symposium on Circuits and Systems, 2018

2017

Robust, self-timed power-on reset circuit for low-voltage applications.

Vivek Nautiyal, Gaurav Singla, Lalit Gupta, Jitendra Dasani, Sagar Dwivedi, Martin Kinkade

Proceedings of the 2017 IFIP/IEEE International Conference on Very Large Scale Integration, 2017

Self-timed Power-on Reset Circuit for Pseudo Dual/Two Port SRAM Used in Low-Voltage IoT Applications.

Vivek Nautiyal, Lalit Gupta, Gaurav Singla, Jitendra Dasani, Sagar Dwivedi, Martin Kinkade

Proceedings of the VLSI-SoC: Opportunities and Challenges Beyond the Internet of Things, 2017

An ultra high density pseudo dual-port SRAM in 16nm FINFET process for graphics processors.

Vivek Nautiyal, Gaurav Singla, Lalit Gupta, Sagar Dwivedi, Martin Kinkade

Proceedings of the 30th IEEE International System-on-Chip Conference, 2017

Charge recycled low power SRAM with integrated write and read assist, for wearable electronics, designed in 7nm FinFET.

Vivek Nautiyal, Gaurav Singla, Satinderjit Singh, Fakhruddin Ali Bohra, Jitendra Dasani, Lalit Gupta, Sagar Dwivedi

Proceedings of the 2017 IEEE/ACM International Symposium on Low Power Electronics and Design, 2017