Safiullah Khan

Orcid: 0000-0001-8342-6928

According to our database1, Safiullah Khan authored at least 15 papers between 2018 and 2024.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

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Bibliography

2024
Towards Optimization of Privacy-Utility Trade-Off Using Similarity and Diversity Based Clustering.
IEEE Trans. Emerg. Top. Comput., 2024

Efficient Soft Core Multiplier for Post Quantum Digital Signatures.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2024

2023
Area-Optimized Constant-Time Hardware Implementation for Polynomial Multiplication.
IEEE Embed. Syst. Lett., March, 2023

Area-Time Efficient Implementation of NIST Lightweight Hash Functions Targeting IoT Applications.
IEEE Internet Things J., 2023

Efficient, Error-Resistant NTT Architectures for CRYSTALS-Kyber FPGA Accelerators.
Proceedings of the 31st IFIP/IEEE International Conference on Very Large Scale Integration, 2023

2022
Network Meddling Detection Using Machine Learning Empowered with Blockchain Technology.
Sensors, 2022

IoMT-Based Osteosarcoma Cancer Detection in Histopathology Images Using Transfer Learning Empowered with Blockchain, Fog Computing, and Edge Computing.
Sensors, 2022

Blockchain-Based Smart Home Networks Security Empowered with Fused Machine Learning.
Sensors, 2022

AEchain: A Lightweight Blockchain for IoT Applications.
IEEE Consumer Electron. Mag., 2022

Toward Privacy Preservation Using Clustering Based Anonymization: Recent Advances and Future Research Outlook.
IEEE Access, 2022

2021
Scalable and Efficient Hardware Architectures for Authenticated Encryption in IoT Applications.
IEEE Internet Things J., 2021

A Flexible Gimli Hardware Implementation in FPGA and Its Application to RFID Authentication Protocols.
IEEE Access, 2021

2020
Cognitive radios real-time implementation on software defined radio for public safety communications.
Telecommun. Syst., 2020

2019
A Dual-Band Metasheet for Asymmetric Microwave Transmission With Polarization Conversion.
IEEE Access, 2019

2018
High-speed FPGA implementation of full-word Montgomery multiplier for ECC applications.
Microprocess. Microsystems, 2018


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