Saeroonter Oh
Orcid: 0000-0003-4281-6879
According to our database1,
Saeroonter Oh
authored at least 2 papers
between 2010 and 2013.
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Bibliography
2013
IEEE Trans. Very Large Scale Integr. Syst., 2013
2010
Modeling and analysis of III-V logic FETs for devices and circuits: Sub-22nm technology III-V SRAM cell design.
Proceedings of the 11th International Symposium on Quality of Electronic Design (ISQED 2010), 2010