Saeideh Shirinzadeh

According to our database, Saeideh Shirinzadeh authored at least 24 papers between 2013 and 2024.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2024

ReSG: A Data Structure for Verification of Majority-based In-memory Computing on ReRAM Crossbars.

Kousik Bhunia, Arighna Deb, Kamalika Datta, Muhammad Hassan, Saeideh Shirinzadeh, Rolf Drechsler

ACM Trans. Embed. Comput. Syst., November, 2024

In-Memory SAT-Solver for Self-Verification of Programmable Memristive Architectures.

Fatemeh Shirinzadeh, Arighna Deb, Saeideh Shirinzadeh, Abhoy Kole, Kamalika Datta, Rolf Drechsler

Proceedings of the 37th International Conference on VLSI Design and 23rd International Conference on Embedded Systems, 2024

2023

Verification of In-Memory Logic Design using ReRAM Crossbars.

Kamalika Datta, Arighna Deb, Fatemeh Shirinzadeh, Abhoy Kole, Saeideh Shirinzadeh, Rolf Drechsler

Proceedings of the 21st IEEE Interregional NEWCAS Conference, 2023

Automated Equivalence Checking Method for Majority Based In-Memory Computing on ReRAM Crossbars.

Arighna Deb, Kamalika Datta, Muhammad Hassan, Saeideh Shirinzadeh, Rolf Drechsler

Proceedings of the 28th Asia and South Pacific Design Automation Conference, 2023

2022

Parallel Computing of Graph-based Functions in ReRAM.

Saman Fröhlich, Saeideh Shirinzadeh, Rolf Drechsler

ACM J. Emerg. Technol. Comput. Syst., 2022

Unlocking High Resolution Arithmetic Operations within Memristive Crossbars for Error Tolerant Applications.

Kamalika Datta, Saman Fröhlich, Saeideh Shirinzadeh, Dev Narayan Yadav, Indranil Sengupta, Rolf Drechsler

Proceedings of the 30th IFIP/IEEE 30th International Conference on Very Large Scale Integration, 2022

Unlocking Sneak Path Analysis in Memristor Based Logic Design Styles.

Kamalika Datta, Saeideh Shirinzadeh, Phrangboklang Lyngton Thangkhiew, Indranil Sengupta, Rolf Drechsler

Proceedings of the 25th Euromicro Conference on Digital System Design, 2022

2020

Multiply-Accumulate Enhanced BDD-Based Logic Synthesis on RRAM Crossbars.

Saman Fröhlich, Saeideh Shirinzadeh, Rolf Drechsler

Proceedings of the IEEE International Symposium on Circuits and Systems, 2020

2019

ComPRIMe: A Compiler for Parallel and Scalable ReRAM-based In-Memory Computing.

Steffen Frerix, Saeideh Shirinzadeh, Saman Fröhlich, Rolf Drechsler

Proceedings of the IEEE/ACM International Symposium on Nanoscale Architectures, 2019

Logic Synthesis for Hybrid CMOS-ReRAM Sequential Circuits.

Saman Fröhlich, Saeideh Shirinzadeh, Rolf Drechsler

Proceedings of the 2019 IEEE Computer Society Annual Symposium on VLSI, 2019

2018

Synthesis and optimization for logic-in-memory computing using memristive devices.

Saeideh Shirinzadeh

PhD thesis, 2018

Logic Synthesis for RRAM-Based In-Memory Computing.

Saeideh Shirinzadeh, Mathias Soeken, Pierre-Emmanuel Gaillardon, Rolf Drechsler

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018

Logic Synthesis for In-memory Computing Using Resistive Memories.

Saeideh Shirinzadeh, Rolf Drechsler

Proceedings of the 2018 IEEE Computer Society Annual Symposium on VLSI, 2018

Logic Design Using Memristors: An Emerging Technology.

Saeideh Shirinzadeh, Kamalika Datta, Rolf Drechsler

Proceedings of the 48th IEEE International Symposium on Multiple-Valued Logic, 2018

2017

Synthesis of optical circuits using binary decision diagrams.

Arighna Deb, Robert Wille, Oliver Keszöcze, Saeideh Shirinzadeh, Rolf Drechsler

Integr., 2017

A PLiM Computer for the Internet of Things.

Mathias Soeken, Pierre-Emmanuel Gaillardon, Saeideh Shirinzadeh, Rolf Drechsler, Giovanni De Micheli

Computer, 2017

An adaptive prioritized <i>ε</i>-preferred evolutionary algorithm for approximate BDD optimization.

Saeideh Shirinzadeh, Mathias Soeken, Daniel Große, Rolf Drechsler

Proceedings of the Genetic and Evolutionary Computation Conference, 2017

Endurance management for resistive Logic-In-Memory computing architectures.

Saeideh Shirinzadeh, Mathias Soeken, Pierre-Emmanuel Gaillardon, Giovanni De Micheli, Rolf Drechsler

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017

2016

Approximate BDD Optimization with Prioritized ε-Preferred Evolutionary Algorithm.

Saeideh Shirinzadeh, Mathias Soeken, Daniel Große, Rolf Drechsler

Proceedings of the Genetic and Evolutionary Computation Conference, 2016

Multi-objective BDD optimization for RRAM based circuit design.

Saeideh Shirinzadeh, Mathias Soeken, Rolf Drechsler

Proceedings of the 2016 IEEE 19th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS), 2016

Fast logic synthesis for RRAM-based in-memory computing using Majority-Inverter Graphs.

Saeideh Shirinzadeh, Mathias Soeken, Pierre-Emmanuel Gaillardon, Rolf Drechsler

Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition, 2016

An MIG-based compiler for programmable logic-in-memory architectures.

Mathias Soeken, Saeideh Shirinzadeh, Pierre-Emmanuel Gaillardon, Luca Gaetano Amarù, Rolf Drechsler, Giovanni De Micheli

Proceedings of the 53rd Annual Design Automation Conference, 2016

2015

Multi-Objective BDD Optimization with Evolutionary Algorithms.

Saeideh Shirinzadeh, Mathias Soeken, Rolf Drechsler

Proceedings of the Genetic and Evolutionary Computation Conference, 2015

2013

High Efficiency Time Redundant Hardened Latch for Reliable Circuit Design.

Rahebeh Niaraki Asli, Saeideh Shirinzadeh

J. Electron. Test., 2013