Saeideh Alinezhad Chamazcoti
Orcid: 0000-0002-0097-6375
According to our database1,
Saeideh Alinezhad Chamazcoti
authored at least 12 papers
between 2014 and 2025.
Collaborative distances:
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Bibliography
2025
J. Syst. Archit., 2025
2024
Bank on Compute-Near-Memory: Design Space Exploration of Processing-Near-Bank Architectures.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., November, 2024
Calibrating DRAMPower Model: A Runtime Perspective from Real-System HPC Measurements.
CoRR, 2024
2023
Exploring Pareto-Optimal Hybrid Main Memory Configurations Using Different Emerging Memories.
IEEE Trans. Circuits Syst. I Regul. Pap., February, 2023
Design Technology co-optimization of 1D-1VCMA to improve read performance for SCM applications.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2023
2022
Design exploration of IGZO diode based VCMA array design for Storage Class Memory Applications.
Proceedings of the 52nd IEEE European Solid-State Device Research Conference, 2022
2019
IEEE Trans. Emerg. Top. Comput., 2019
Parloom: A New Low-Power Set-Associative Instruction Cache Architecture Utilizing Enhanced Counting Bloom Filter and Partial Tags.
J. Circuits Syst. Comput., 2019
2017
IEEE Trans. Multi Scale Comput. Syst., 2017
2016
Microprocess. Microsystems, 2016
2015
Microelectron. Reliab., 2015
2014
Proceedings of the 20th IEEE Pacific Rim International Symposium on Dependable Computing, 2014