Saeid Nooshabadi

Orcid: 0000-0001-8596-1350

According to our database1, Saeid Nooshabadi authored at least 131 papers between 1997 and 2023.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Bibliography

2023
Automotive Radar-Based Hitch Angle Tracking Technique for Trailer Backup Assistant Systems.
IEEE Trans. Intell. Veh., February, 2023

2022
Hitch Angle Estimation for Trailer Backup System - An Object Detection and Tracking Approach.
IEEE Trans. Instrum. Meas., 2022

Mobile-PolypNet: Lightweight Colon Polyp Segmentation Network for Low-Resource Settings.
J. Imaging, 2022

Efficient Density Estimation for High-Dimensional Data.
IEEE Access, 2022

2021
Extrinsic Radar Calibration With Overlapping FoV and Hitch Ball Position Estimation.
IEEE Trans. Instrum. Meas., 2021

Extrinsic Calibration of Radar Mount Position and Orientation With Multiple Target Configurations.
IEEE Trans. Instrum. Meas., 2021

Trailer angle estimation using radar point clouds.
Signal Process., 2021

Exploiting Block Structures of KKT Matrices for Efficient Solution of Convex Optimization Problems.
IEEE Access, 2021

2020
Nonparametric Density Estimation Using Copula Transform, Bayesian Sequential Partitioning, and Diffusion-Based Kernel Estimator.
IEEE Trans. Knowl. Data Eng., 2020

Multi-level complexity reduction for HEVC multiview coding.
J. Real Time Image Process., 2020

Accelerated Density-Based Clustering using Bayesian Sequential Partitioning.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2020

2019
Parallel hybrid bispectrum-multi-frame blind deconvolution image reconstruction technique.
J. Real Time Image Process., 2019

High-dimensional image descriptor matching using highly parallel KD-tree construction and approximate nearest neighbor search.
J. Parallel Distributed Comput., 2019

Versatile CMOS Current Conveyor for Digital VLSI Systems with Low-Voltage Power Supply.
J. Low Power Electron., 2019

Online density estimation over high-dimensional stationary and non-stationary data streams.
Data Knowl. Eng., 2019

Current Mirror Based Low Voltage Single Supply CMOS Level up-Shifter.
Proceedings of the 62nd IEEE International Midwest Symposium on Circuits and Systems, 2019

Online Density Estimation Over High-Dimensional Data Streams.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2019

Progressive Binary Partitioning for Performance Improvement in Multivariate Density Estimation.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2019

High Performance CMOS Level up Conversion for Systems with Low-Voltage Power Supply.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2019

2018
Highly Reliable Decision-Making Using Reliability Factor Feedback for Factory Condition Monitoring via WSNs.
Wirel. Commun. Mob. Comput., 2018

High performance CMOS level up shifter with full-scale 1.2 V output voltage.
Microelectron. J., 2018

Low Swing Charge Recycling Driver for On-Chip Interconnect.
J. Low Power Electron., 2018

Locating and Disregarding the Information from Compromised Sensors in a WSN.
Proceedings of the 9th IEEE Annual Ubiquitous Computing, 2018

Sensor Cooperation and Decision Fusion to Improve Detection in Cognitive Radio Spectrum Sensing.
Proceedings of the 9th IEEE Annual Ubiquitous Computing, 2018

2017
Circular Sphere Decoding: A Low Complexity Detection for MIMO Systems With General Two-dimensional Signal Constellations.
IEEE Trans. Veh. Technol., 2017

High performance single supply CMOS 0.45-1 V input to 1.1 V output level up shifter.
Microelectron. J., 2017

Massive parallelization of approximate nearest neighbor search on KD-tree for high-dimensional image descriptor matching.
J. Vis. Commun. Image Represent., 2017

1.2 V Single Supply CMOS Level-Up Shifter for Low Energy Systems.
J. Low Power Electron., 2017

Low Energy Bus Design with Error Tolerant Coding.
J. Low Power Electron., 2017

Structure-Aware Linear Solver for Realtime Convex Optimization for Embedded Systems.
IEEE Embed. Syst. Lett., 2017

Efficient data structures for density estimation for large high-dimensional data.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2017

H.265/HEVC encoder optimization with parallel-efficient algorithm and QP-based early termination.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2017

Single supply CMOS Up level shifter for dual voltage system.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2017

Analysis and design of serial error correction code with crosstalk avoidance technique.
Proceedings of the 30th IEEE Canadian Conference on Electrical and Computer Engineering, 2017

2016
Parallel Multiview Video Coding Exploiting Group of Pictures Level Parallelism.
IEEE Trans. Parallel Distributed Syst., 2016

A Scalable Massively Parallel Motion and Disparity Estimation Scheme for Multiview Video Coding.
IEEE Trans. Circuits Syst. Video Technol., 2016

Parallel hybrid bispectrum-multiframe blind deconvolution algorithm for horizontal imaging.
Proceedings of the 14th IEEE International New Circuits and Systems Conference, 2016

Parallel randomized KD-tree forest on GPU cluster for image descriptor matching.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2016

Decision Zone-Based Parallel Fast Motion and Disparity Estimation Scheme for Multiview Coding.
Proceedings of the 2016 Data Compression Conference, 2016

Massively Efficient Motion Estimation by Exploiting Inter-Pixel Similarities.
Proceedings of the 2016 Data Compression Conference, 2016

Opportunities for High-Level Parallelism in Multiview Video Coding.
Proceedings of the 2016 Data Compression Conference, 2016

2015
G-SHOT: GPU accelerated 3D local descriptor for surface matching.
J. Vis. Commun. Image Represent., 2015

Massively parallel KD-tree construction and nearest neighbor search algorithms.
Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015

A 3D local descriptor SHOT on massively parallel processors.
Proceedings of the IEEE International Conference on Consumer Electronics, 2015

High performance single supply CMOS inverter level up shifter for multi: supply voltages domains.
Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015

2014
Complex Valued Sphere Decoding with Element-wise Selective Prescreening for General Two-dimensional Signal Constellations.
CoRR, 2014

Node Synchronization in a Wireless Sensor Network Using Unreliable GPS Signals.
Proceedings of the 2014 IEEE Military Communications Conference, 2014

A novel decoder architecture for error resilient JPEG2000 applications based on MQ arithmetic.
Proceedings of the IEEE International Symposium on Circuits and Systemss, 2014

Signal alignment for secure underwater coordinated multipoint transmissions.
Proceedings of the IEEE Conference on Communications and Network Security, 2014

2013
Forward error correction with Raptor GF(2) and GF(256) codes on GPU.
IEEE Trans. Consumer Electron., 2013

A 2.63 Mbit/s VLSI Implementation of SISO Arithmetic Decoders for High Performance Joint Source Channel Codes.
IEEE Trans. Circuits Syst. I Regul. Pap., 2013

Forward error correction with RaptorQ code on GPU.
Proceedings of the 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), 2013

GPU accelerated motion and disparity estimations for multiview coding.
Proceedings of the IEEE International Conference on Image Processing, 2013

2012
Efficient GF(256) raptor code decoding for multimedia broadcast/multicast services and consumer terminals.
IEEE Trans. Consumer Electron., 2012

Analysis and design of coding and interleaving in a MIMO-OFDM communication system.
IEEE Trans. Consumer Electron., 2012

A 5 MSps 13.25µW 8-bit SAR ADC with single-ended or differential input.
Microelectron. J., 2012

Editorial.
Microelectron. J., 2012

Decoding of Raptor codes on embedded systems.
Microprocess. Microsystems, 2012

Optimization of On-Chip Interconnect Signaling for Low Energy and High Performance.
J. Low Power Electron., 2012

Guest Editor's Introduction.
J. Circuits Syst. Comput., 2012

Very-large-scale integration hardware implementation of adaptive space-time coding/spatial multiplexing switching.
IET Commun., 2012

A 749nW 1MSps 8-bit SAR ADC at 0.5V employing boosted switches.
Proceedings of the 19th IEEE International Conference on Electronics, Circuits and Systems, 2012

2011
Implementation and Evaluation of Raptor Codes on Embedded Systems.
IEEE Trans. Computers, 2011

Efficient Incremental Raptor Decoding Over BEC for 3GPP MBMS and DVB IP-Datacast Services.
IEEE Trans. Broadcast., 2011

An energy-efficient 1MSps 7µW 11.9fJ/conversion step 7pJ/sample 10-bit SAR ADC in 90nm.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2011), 2011

Predicting the pruning potential in sphere decoding for multiple-input multiple-output detection.
Proceedings of the Conference Record of the Forty Fifth Asilomar Conference on Signals, 2011

2010
MBMS raptor codes design trade-offs for IPTV.
IEEE Trans. Consumer Electron., 2010

Strategies for the design of raptor decoding in broadcast/multicast delivery systems.
IEEE Trans. Consumer Electron., 2010

Design of a Tunable All-Digital UWB Pulse Generator CMOS Chip for Wireless Endoscope.
IEEE Trans. Biomed. Circuits Syst., 2010

Application of genetic algorithm in computing the tradeoffs between power consumption versus delay in digital integrated circuit design.
Microelectron. J., 2010

A Genetic Algorithm Methodology to Find the Maximum Datapath Coverage for Combinational Logic Circuits.
J. Circuits Syst. Comput., 2010

Application of Mixed Integer Linear Programming in the Generation of Vectors with Maximum Datapath Coverage for Combinational Logic Circuits.
J. Circuits Syst. Comput., 2010

An adaptive Space-Time Coding / Spatial Multiplexing detector on FPGA.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010

Parallel scalable hardware architecture for hard Raptor decoder.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010

Low-energy multi-path adiabatic CMOS driver for low-energy system applications with large capacitive load.
Proceedings of the 17th IEEE International Conference on Electronics, 2010

An energy-efficient successive approximation register analog to digital converter in 180nm.
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2010

2009
CMOS Driver-Receiver Pair for Low-Swing Signaling for Low Energy On-Chip Interconnects.
IEEE Trans. Very Large Scale Integr. Syst., 2009

Efficient Implementation Techniques for Maximum Likelihood-Based Error Correction for JPEG2000.
IEEE Trans. Circuits Syst. Video Technol., 2009

Design and Analysis of System on a Chip Encoder for JPEG2000.
IEEE Trans. Circuits Syst. Video Technol., 2009

CMOS design and analysis of low-voltage signaling methodology for energy efficient on-chip interconnects.
Microelectron. J., 2009

A geometric approach to register transfer level satisfiability.
Proceedings of the 10th International Symposium on Quality of Electronic Design (ISQED 2009), 2009

An optimization strategy for low energy and high performance for the on-chip interconnect signalling.
Proceedings of the 2009 International Symposium on Low Power Electronics and Design, 2009

Analysis and Comparison of High Performance CMOS Adiabatic Drivers.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2009), 2009

Analysis and Design of Memoryless Interconnect Encoding Scheme.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2009), 2009

A feasible VLSI engine for soft-input-soft-output for joint source channel codes.
Proceedings of the International Conference on Image Processing, 2009

Bootstrapped Adiabatic Complementary Pass-Transistor Logic Driver Circuit for Large Capacitive Load and Low-energy Applications.
Proceedings of the 12th Euromicro Conference on Digital System Design, 2009

High Performance CMOS 2-input NAND Based on Low-race Split-level Charge-recycling Pass-transistor Logic.
Proceedings of the 12th Euromicro Conference on Digital System Design, 2009

High Performance Bootstrapped CMOS Dual Supply Level Shifter for 0.5V Input and 1V Output.
Proceedings of the 12th Euromicro Conference on Digital System Design, 2009

2008
Efficient Interfacing of DWT and EBCOT in JPEG2000.
IEEE Trans. Circuits Syst. Video Technol., 2008

Design methodology for configurable analog to digital conversion using support vector machines.
Microelectron. J., 2008

Error resilient JPEG2000 decoding for wireless applications.
Proceedings of the International Conference on Image Processing, 2008

Implementation of reconfigurable SHA-2 hardware core.
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2008

A CMOS adiabatic inverter operating with a single clock power supply to reduce non-adiabatic loss.
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2008

Low energy CMOS true single phase power supply clocking adiabatic differential cascode voltage switch logic circuit.
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2008

2007
Novel Distortion Estimation Technique for Hardware-Based JPEG2000 Encoder System.
IEEE Trans. Circuits Syst. Video Technol., 2007

Analysis of High-Performance Fast Feedthrough Logic Families in CMOS.
IEEE Trans. Circuits Syst. II Express Briefs, 2007

High performance low power CMOS dynamic logic for arithmetic circuits.
Microelectron. J., 2007

Efficient Data Transfer Techniques and VLSI architecture for DWT-Block Coder Integration of JPEG2000 Encoder.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007

Adaptive Low/High Voltage Swing CMOS Driver for On-Chip Interconnects.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007

Analysis of Multiple Parallel Block Coding in JPEG2000.
Proceedings of the International Conference on Image Processing, 2007

High performance bootstrapped CMOS low to high-swing level-converter for on-chip interconnects.
Proceedings of the 18th European Conference on Circuit Theory and Design, 2007

Efficient CMOS driver-receiver pair with low-swing signaling for on-chip interconnects.
Proceedings of the 18th European Conference on Circuit Theory and Design, 2007

2006
Modernization of teaching in embedded systems design - an international collaborative project.
IEEE Trans. Educ., 2006

Realizing Low-Cost High-Throughput General-Purpose Block Encoder for JPEG2000.
IEEE Trans. Circuits Syst. Video Technol., 2006

A Single-Capacitor Bootstrapped Power-Efficient CMOS Driver.
IEEE Trans. Circuits Syst. II Express Briefs, 2006

Concurrency techniques for arithmetic coding in JPEG2000.
IEEE Trans. Circuits Syst. I Regul. Pap., 2006

Low Power and High Performance Arithmetic Circuits in Feedthrough CMOS Logic Family for Low Power Applications.
J. Low Power Electron., 2006

VLSI architecture for 4×4 16-QAM V-BLAST decoder.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

Near-Optimal Low-Cost Distortion Estimation Technique for JPEG2000 Encoder.
Proceedings of the 2006 IEEE International Conference on Acoustics Speech and Signal Processing, 2006

Bootstrapped full-swing CMOS driver for low supply voltage operation.
Proceedings of the Conference on Design, Automation and Test in Europe, 2006

Low Power Bootstrapped CMOS Differential Cross Coupled Driver.
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems 2006, 2006

2005
Concurrent Symbol Processing Capable VLSI Architecture for Bit Plane Coder of JPEG2000.
IEICE Trans. Inf. Syst., 2005

3D-SoftChip: A Novel 3D Vertically Integrated Adaptive Computing System.
Proceedings of the VLSI-SoC: From Systems To Silicon, 2005

VLSI hardware design of QR-factorizer for a V-BLAST detector.
Proceedings of the Eighth International Symposium on Signal Processing and Its Applications, 2005

Opcode encoding for low power embedded systems.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

Optimal 2 sub-bank memory architecture for bit plane coder of JPEG2000.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

Efficient VLSI architecture for buffer used in EBCOT of JPEG2000 encoder.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

Reduced latency arithmetic decoder for JPEG2000 block decoding.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

2004
Fast feedthrough logic: a high performance logic family for GaAs.
IEEE Trans. Circuits Syst. I Regul. Pap., 2004

Design and Performance of Asymmetric Turbo Coded Hybrid-ARQ.
Proceedings of the Telecommunications and Networking, 2004

Improved throughput arithmetic coder for jpeg2000.
Proceedings of the 2004 International Conference on Image Processing, 2004

2003
Memory efficient pass-parallel architecture for JPEG2000 encoding.
Proceedings of the Seventh International Symposium on Signal Processing and Its Applications, 2003

2001
Efficient computation of the area/power consumption versus delay tradeoff curve for circuit critical path optimization.
Proceedings of the 2001 International Symposium on Circuits and Systems, 2001

Modelling of effects of temperature profile in the MOS transistor characteristics.
Proceedings of the 2001 International Symposium on Circuits and Systems, 2001

A compact layout technique to minimize high frequency switching effects in high speed circuits.
Proceedings of the 2001 International Symposium on Circuits and Systems, 2001

2000
A Single Phase Latch for High Speed GaAs Domino Circuits.
Proceedings of the 2000 Design, 2000

1999
A novel latch design technique for high speed GaAs circuits.
Proceedings of the 6th IEEE International Conference on Electronics, Circuits and Systems, 1999

High Speed GaAs Subsystem Design using Feed Through Logic.
Proceedings of the 1999 Design, 1999

1998
Current Mode Ternary D/A Converter.
Proceedings of the 11th International Conference on VLSI Design (VLSI Design 1991), 1998

1997
Micropipeline Architecture for Multiplier-less FIR Filters.
Proceedings of the 10th International Conference on VLSI Design (VLSI Design 1997), 1997

An Asynchronous Morphological Processor for Multi-Media Applications.
Proceedings of the 10th International Conference on VLSI Design (VLSI Design 1997), 1997


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