Saeid Gorgin

Orcid: 0000-0001-5898-4872

Affiliations:
  • Iranian Research Organization for Science and Technology (IROST), Tehran, Iran


According to our database1, Saeid Gorgin authored at least 68 papers between 2006 and 2025.

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Bibliography

2025
Efficient hardware accelerators for k-nearest neighbors classification using most significant digit first arithmetic.
J. Supercomput., January, 2025

Poster: Integration of Wearable and Affective Computing via Abstraction and Decision Fusion Architecture.
Proceedings of the 25th IEEE International Symposium on a World of Wireless, 2025

2024
Low-cost constant time signed digit selection for most significant bit first multiplication.
Microprocess. Microsystems, 2024

An ultra-low-computation model for understanding sign languages.
Expert Syst. Appl., 2024

Enhancing Computational Efficiency in Intensive Domains via Redundant Residue Number Systems.
CoRR, 2024

The Reversing Machine: Reconstructing Memory Assumptions.
CoRR, 2024

Abstraction and decision fusion architecture for resource-aware image understanding with application on handwriting character classification.
Appl. Soft Comput., 2024

DSLR-CNN: Efficient CNN Acceleration Using Digit-Serial Left-to-Right Arithmetic.
IEEE Access, 2024

GELU-MSDF: A Hardware Accelerator for Transformer's GELU Activation Function Using Most Significant Digit First Computation.
Proceedings of the 37th IEEE International System-on-Chip Conference, 2024

Hardware Design Space Exploration in High-Level Synthesis Backend Featuring Online Arithmetic.
Proceedings of the 37th IEEE International System-on-Chip Conference, 2024

Enhancing Efficiency in Computational Intensive Domains via Redundant Residue Number Systems.
Proceedings of the 21st International SoC Design Conference, 2024

2023
A Generalized Residue Number System Design Approach for Ultralow-Power Arithmetic Circuits Based on Deterministic Bit-Streams.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., November, 2023

Low Latency and High Throughput Pipelined Online Adder for Streaming Inner Product.
J. Signal Process. Syst., July, 2023

Fuzzy logic-based DDoS attacks and network traffic anomaly detection methods: Classification, overview, and future perspectives.
Inf. Sci., May, 2023

FPGA-orthopoly: a hardware implementation of orthogonal polynomials.
Eng. Comput., 2023

A new energy-efficient and temperature-aware routing protocol based on fuzzy logic for multi-WBANs.
Ad Hoc Networks, 2023

Dependable DNN Accelerator for Safety-Critical Systems: A Review on the Aging Perspective.
IEEE Access, 2023

Modulo-(2<sup>q</sup> - 3) Multiplication with Fully Modular Partial Product Generation and Reduction.
Proceedings of the 30th IEEE Symposium on Computer Arithmetic, 2023

MSDF-SVM: Advantage of Most Significant Digit First Arithmetic for SVM Realization.
Proceedings of the 57th Asilomar Conference on Signals, Systems, and Computers, ACSSC 2023, Pacific Grove, CA, USA, October 29, 2023

An Efficient Dot-Product Unit Based on Online Arithmetic for Variable Precision Applications.
Proceedings of the 57th Asilomar Conference on Signals, Systems, and Computers, ACSSC 2023, Pacific Grove, CA, USA, October 29, 2023

2022
An improved discrete harris hawk optimization algorithm for efficient workflow scheduling in multi-fog computing.
Sustain. Comput. Informatics Syst., 2022

HyperDbg: Reinventing Hardware-Assisted Debugging.
CoRR, 2022

A Practical Energy/Power Reduction Approach for Parallel Decimal Multiplier.
IEEE Access, 2022

kNN-MSDF: A Hardware Accelerator for k-Nearest Neighbors Using Most Significant Digit First Computation.
Proceedings of the 35th IEEE International System-on-Chip Conference, 2022

Ice Detection on Edge Device Based on Most Significant Digit First SVM.
Proceedings of the 6th International Conference on Video and Image Processing, 2022

Hardware Efficient FIR Filter Architectures Using Accurate Unary Stochastic Computing.
Proceedings of the IEEE 40th International Conference on Computer Design, 2022

An Energy-Efficient K-means Clustering FPGA Accelerator via Most-Significant Digit First Arithmetic.
Proceedings of the International Conference on Field-Programmable Technology, 2022

An Efficient FPGA Implementation of k-Nearest Neighbors via Online Arithmetic.
Proceedings of the 30th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2022

HyperDbg: Reinventing Hardware-Assisted Debugging.
Proceedings of the 2022 ACM SIGSAC Conference on Computer and Communications Security, 2022

2021
A High-throughput Parallel Viterbi Algorithm via Bitslicing.
ACM Trans. Parallel Comput., 2021

High-Performance Deterministic Stochastic Computing Using Residue Number System.
IEEE Des. Test, 2021

Unlucky Explorer: A Complete non-Overlapping Map Exploration.
Proceedings of the WSSE 2021: The 3rd World Symposium on Software Engineering, Xiamen, China, September 24, 2021

On Using Monte-Carlo Tree Search to Solve Puzzles.
Proceedings of the ICCTA 2021: 7th International Conference on Computer Technology Applications, Vienna, Austria, July 13, 2021

A TSX-Based KASLR Break: Bypassing UMIP and Descriptor-Table Exiting.
Proceedings of the Risks and Security of Internet and Systems, 2021

2020
Unlucky Explorer: A Complete non-Overlapping Map Exploration.
CoRR, 2020

A Way Around UMIP and Descriptor-Table Exiting via TSX-based Side-Channel Attack.
CoRR, 2020

A fuzzy irregular cellular automata-based method for the vertex colouring problem.
Connect. Sci., 2020

On the Resilience of Deep Learning for Reduced-voltage FPGAs.
Proceedings of the 28th Euromicro International Conference on Parallel, 2020

BSRNG: A High Throughput Parallel BitSliced Approach for Random Number Generators.
Proceedings of the ICPP Workshops '20: Workshops, Edmonton, AB, Canada, August 17-20, 2020, 2020

2019
Accuracy and availability modeling of social networks for Internet of Things event detection applications.
Wirel. Networks, 2019

Fast AES Implementation: A High-Throughput Bitsliced Approach.
IEEE Trans. Parallel Distributed Syst., 2019

Decentralized Cooperative Communication-less Multi-Agent Task Assignment with Monte-Carlo Tree Search.
CoRR, 2019

High-performance Cryptographically Secure Pseudo-random Number Generation via Bitslicing.
CoRR, 2019

Data-Parallel Computational Model for Next Generation Sequencing on Commodity Clusters.
Proceedings of the Parallel Computing Technologies, 2019

Multi-Agent non-Overlapping Pathfinding with Monte-Carlo Tree Search.
Proceedings of the IEEE Conference on Games, 2019

Using Residue Number Systems to Accelerate Deterministic Bit-stream Multiplication.
Proceedings of the 30th IEEE International Conference on Application-specific Systems, 2019

2018
A high-performance and energy-efficient exhaustive key search approach via GPU on DES-like cryptosystems.
J. Supercomput., 2018

2017
Sign-Magnitude Encoding for Efficient VLSI Realization of Decimal Multiplication.
IEEE Trans. Very Large Scale Integr. Syst., 2017

Sequence Similarity Parallelization over Heterogeneous Computer Clusters Using Data Parallel Programming Model.
Scalable Comput. Pract. Exp., 2017

Design of non-restoring divider in quantum-dot cellular automata technology.
IET Circuits Devices Syst., 2017

2016
An efficient design of full adder in quantum-dot cellular automata (QCA) technology.
Microelectron. J., 2016

2015
Comment on "High Speed Parallel Decimal Multiplication With Redundant Internal Encodings".
IEEE Trans. Computers, 2015

Efficient continuous skyline computation on multi-core processors based on Manhattan distance.
Proceedings of the 13. ACM/IEEE International Conference on Formal Methods and Models for Codesign, 2015

2014
A comparative study of energy/power consumption in parallel decimal multipliers.
Microelectron. J., 2014

Efficient ASIC and FPGA Implementation of Binary-Coded Decimal Digit Multipliers.
Circuits Syst. Signal Process., 2014

A Review on Modern Distributed Computing Paradigms: Cloud Computing, Jungle Computing and Fog Computing.
J. Comput. Inf. Technol., 2014

A fast emulator for ARM-based embedded systems.
Proceedings of the Twelfth ACM/IEEE International Conference on Formal Methods and Models for Codesign, 2014

Cost-efficient implementation of k-NN algorithm on multi-core processors.
Proceedings of the Twelfth ACM/IEEE International Conference on Formal Methods and Models for Codesign, 2014

2013
Fast and adaptive BP-based multi-core implementation for stereo matching.
Proceedings of the 11th ACM/IEEE International Conference on Formal Methods and Models for Codesign, 2013

2011
GPU-based NoC simulator.
Proceedings of the 9th IEEE/ACM International Conference on Formal Methods and Models for Codesign, 2011

A Family of High Radix Signed Digit Adders.
Proceedings of the 20th IEEE Symposium on Computer Arithmetic, 2011

2010
Redundant-Digit Floating-Point Addition Scheme Based on a Stored Rounding Value.
IEEE Trans. Computers, 2010

An improved maximally redundant signed digit adder.
Comput. Electr. Eng., 2010

2009
A fully redundant decimal adder and its application in parallel decimal multipliers.
Microelectron. J., 2009

Fully Redundant Decimal Arithmetic.
Proceedings of the 19th IEEE Symposium on Computer Arithmetic, 2009

2008
A Nonspeculative Maximally Redundant Signed Digit Adder.
Proceedings of the Advances in Computer Science and Engineering, 2008

2007
Reversible Barrel Shifters.
Proceedings of the 2007 IEEE/ACS International Conference on Computer Systems and Applications (AICCSA 2007), 2007

2006
Reversible Implementation of Densely-Packed-Decimal Converter to and from Binary-Coded-Decimal Format Using in IEEE-754R.
Proceedings of the 9th International Conference in Information Technology, 2006


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