Saeed Ur Reehman
According to our database1,
Saeed Ur Reehman
authored at least 3 papers
between 2014 and 2015.
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Bibliography
2015
In-place memory mapping approach for optimized parallel hardware interleaver architectures.
Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015
2014
Conception d'architectures d'entrelaceurs parallèles pour les décodeurs de Turbo-Codes et de LDPC. (Designing Optimized Parallel Interleaver Architectures For Turbo And Ldpc Decoders).
PhD thesis, 2014
A memory mapping approach based on network customization to design conflict-free parallel hardware architectures.
Proceedings of the Great Lakes Symposium on VLSI 2014, GLSVLSI '14, Houston, TX, USA - May 21, 2014