Sadulla Shaik

According to our database, Sadulla Shaik authored at least 10 papers between 2014 and 2024.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of five.

2024

Design and analysis of a novel compact quaternary adder.

S. Lakshmanachari, Sadulla Shaik, G. S. R. Satyanarayana, Vallabhuni Vijay, Chandra Shaker Pittala, K. Indira, S. Swathi

Int. J. Syst. Assur. Eng. Manag., July, 2024

State-of-art design: data selectors using quantum-dot cellular automata.

Menda Sreevani, Vallabhuni Vijay, Kancharapu Chaitanya, Chelle Radhika, Nandi Manjula, D. Radha Krishna Koushik, B. Sai Venumadhav, T. Sai Jaideep, Chandra Shaker Pittala, Sadulla Shaik

Int. J. Syst. Assur. Eng. Manag., March, 2024

1-bit full adder design using next generation semiconductor devices and performance benchmarking at low supply voltages.

S. Lakshmanachari, Sadulla Shaik, G. S. R. Satyanarayana, Inapudi Vasavi, Vallabhuni Vijay, Chandra Shaker Pittala

Int. J. Syst. Assur. Eng. Manag., March, 2024

2023

Design and performance analysis of low power and energy-efficient vedic multipliers.

Sadulla Shaik, Satish Kanapala, Vallabhuni Vijay, Chandra Shaker Pittala

Int. J. Syst. Assur. Eng. Manag., June, 2023

2020

Device-Circuit Interaction and Performance Benchmarking of Tunnel Transistor-Based Ex-OR Gates for Energy Efficient Computing.

Sadulla Shaik

J. Circuits Syst. Comput., 2020

2019

Applying several soft computing techniques for prediction of bearing capacity of driven piles.

Sadulla Shaik, Kalva Sri Rama Krishna, Mazhar Abbas, Munir Ahmed, Dinesh Mavaluru

Eng. Comput., 2019

2018

Tunnel Transistor-Based Reliable and Energy Efficient Computing Architectures with Circuit and Architectural Co-Design at Low VDD.

Sadulla Shaik, Kalva Sri Rama Krishna, Ramesh Vaddi

J. Circuits Syst. Comput., 2018

2017

Performance benchmarking of tunnel transistors for energy efficient 4-bit adder architectures at low V_DD.

Sadulla Shaik, Kalva Sri Rama Krishna

Electron. Gov. an Int. J., 2017

2016

Circuit and Architectural Co-design for Reliable Adder Cells with Steep Slope Tunnel Transistors for Energy Efficient Computing.

Sadulla Shaik, Kalva Sri Rama Krishna, Ramesh Vaddi

Proceedings of the 29th International Conference on VLSI Design and 15th International Conference on Embedded Systems, 2016

2014

Tunnel FET based low voltage static vs dynamic logic families for energy efficiency.

Kasturi Subramanyam, Sadulla Shaik, Ramesh Vaddi

Proceedings of the 18th International Symposium on VLSI Design and Test, 2014