Sadulla Shaik

Orcid: 0000-0003-3119-8905

According to our database1, Sadulla Shaik authored at least 10 papers between 2014 and 2024.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of five.

Timeline

Legend:

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PhD thesis 
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Links

On csauthors.net:

Bibliography

2024
Design and analysis of a novel compact quaternary adder.
Int. J. Syst. Assur. Eng. Manag., July, 2024

State-of-art design: data selectors using quantum-dot cellular automata.
Int. J. Syst. Assur. Eng. Manag., March, 2024

1-bit full adder design using next generation semiconductor devices and performance benchmarking at low supply voltages.
Int. J. Syst. Assur. Eng. Manag., March, 2024

2023
Design and performance analysis of low power and energy-efficient vedic multipliers.
Int. J. Syst. Assur. Eng. Manag., June, 2023

2020
Device-Circuit Interaction and Performance Benchmarking of Tunnel Transistor-Based Ex-OR Gates for Energy Efficient Computing.
J. Circuits Syst. Comput., 2020

2019
Applying several soft computing techniques for prediction of bearing capacity of driven piles.
Eng. Comput., 2019

2018
Tunnel Transistor-Based Reliable and Energy Efficient Computing Architectures with Circuit and Architectural Co-Design at Low VDD.
J. Circuits Syst. Comput., 2018

2017
Performance benchmarking of tunnel transistors for energy efficient 4-bit adder architectures at low V<sub>DD</sub>.
Electron. Gov. an Int. J., 2017

2016
Circuit and Architectural Co-design for Reliable Adder Cells with Steep Slope Tunnel Transistors for Energy Efficient Computing.
Proceedings of the 29th International Conference on VLSI Design and 15th International Conference on Embedded Systems, 2016

2014
Tunnel FET based low voltage static vs dynamic logic families for energy efficiency.
Proceedings of the 18th International Symposium on VLSI Design and Test, 2014


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