Sadeka Ali

According to our database, Sadeka Ali authored at least 4 papers between 2004 and 2006.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2006

Process tolerant calibration circuit for PLL applications with BIST.

Quentin Diduck, John C. Liobe, Sadeka Ali, Martin Margala

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

A 2.4-GHz auto-calibration frequency synthesizer with on-chip built-in-self-test solution.

Sadeka Ali, Martin Margala

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

2005

A High Frequency, Low Jitter Auto-Calibration Phase-Locked Loop with Built-in-Self-Test.

Sadeka Ali, Gregory Briggs, Martin Margala

Proceedings of the 20th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2005), 2005

2004

A 5.1-GHz CMOS PLL based integer-N frequency synthesizer with ripple-free control voltage and improved acquisition time.

Sadeka Ali, Martin Margala

Proceedings of the 2004 International Symposium on Circuits and Systems, 2004