Sadegh Yazdanshenas

According to our database, Sadegh Yazdanshenas authored at least 17 papers between 2014 and 2020.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of three.

2020

FPGA Logic Block Architectures for Efficient Deep Learning Inference.

Mohamed Eldafrawy, Andrew Boutros, Sadegh Yazdanshenas, Vaughn Betz

ACM Trans. Reconfigurable Technol. Syst., 2020

2019

The Costs of Confidentiality in Virtualized FPGAs.

Sadegh Yazdanshenas, Vaughn Betz

IEEE Trans. Very Large Scale Integr. Syst., 2019

COFFE 2: Automatic Modelling and Optimization of Complex and Heterogeneous FPGA Architectures.

Sadegh Yazdanshenas, Vaughn Betz

ACM Trans. Reconfigurable Technol. Syst., 2019

Math Doesn't Have to be Hard: Logic Block Architectures to Enhance Low-Precision Multiply-Accumulate on FPGAs.

Andrew Boutros, Mohamed Eldafrawy, Sadegh Yazdanshenas, Vaughn Betz

Proceedings of the 2019 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2019

2018

Enhancing FPGAs with Magnetic Tunnel Junction-Based Block RAMs.

Kosuke Tatsumura, Sadegh Yazdanshenas, Vaughn Betz

ACM Trans. Reconfigurable Technol. Syst., 2018

You Cannot Improve What You Do not Measure: FPGA vs. ASIC Efficiency Gaps for Convolutional Neural Network Inference.

Andrew Boutros, Sadegh Yazdanshenas, Vaughn Betz

ACM Trans. Reconfigurable Technol. Syst., 2018

Interconnect Solutions for Virtualized Field-Programmable Gate Arrays.

Sadegh Yazdanshenas, Vaughn Betz

IEEE Access, 2018

Improving Confidentiality in Virtualized FPGAs.

Sadegh Yazdanshenas, Vaughn Betz

Proceedings of the International Conference on Field-Programmable Technology, 2018

Embracing Diversity: Enhanced DSP Blocks for Low-Precision Deep Learning on FPGAs.

Andrew Boutros, Sadegh Yazdanshenas, Vaughn Betz

Proceedings of the 28th International Conference on Field Programmable Logic and Applications, 2018

2017

Automatic circuit design and modelling for heterogeneous FPGAs.

Sadegh Yazdanshenas, Vaughn Betz

Proceedings of the International Conference on Field Programmable Technology, 2017

Quantifying and mitigating the costs of FPGA virtualization.

Sadegh Yazdanshenas, Vaughn Betz

Proceedings of the 27th International Conference on Field Programmable Logic and Applications, 2017

Don't Forget the Memory: Automatic Block RAM Modelling, Optimization, and Architecture Exploration.

Sadegh Yazdanshenas, Kosuke Tatsumura, Vaughn Betz

Proceedings of the 2017 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2017

2016

Designing Low Power and Durable Digital Blocks Using Shadow Nanoelectromechanical Relays.

Sadegh Yazdanshenas, Behnam Khaleghi, Paolo Ienne, Hossein Asadi

IEEE Trans. Very Large Scale Integr. Syst., 2016

High density, low energy, magnetic tunnel junction based block RAMs for memory-rich FPGAs.

Kosuke Tatsumura, Sadegh Yazdanshenas, Vaughn Betz

Proceedings of the 2016 International Conference on Field-Programmable Technology, 2016

2015

A Scalable Dependability Scheme for Routing Fabric of SRAM-Based Reconfigurable Devices.

Sadegh Yazdanshenas, Hossein Asadi, Behnam Khaleghi

IEEE Trans. Very Large Scale Integr. Syst., 2015

2014

Fine-Grained Architecture in Dark Silicon Era for SRAM-Based Reconfigurable Devices.

Sadegh Yazdanshenas, Hossein Asadi

IEEE Trans. Circuits Syst. II Express Briefs, 2014

Coding Last Level STT-RAM Cache for High Endurance and Low Power.

Sadegh Yazdanshenas, Marzieh Ranjbar Pirbasti, Mahdi Fazeli, Ahmad Patooghy

IEEE Comput. Archit. Lett., 2014