Sadaaki Masuoka
According to our database1,
Sadaaki Masuoka
authored at least 4 papers
between 2000 and 2005.
Collaborative distances:
Collaborative distances:
Timeline
2000
2001
2002
2003
2004
2005
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Legend:
Book In proceedings Article PhD thesis Dataset OtherLinks
On csauthors.net:
Bibliography
2005
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005
2001
An ultrahigh-density high-speed loadless four-transistor SRAM macro with twisted bitline architecture and triple-well shield.
IEEE J. Solid State Circuits, 2001
2000
IEEE J. Solid State Circuits, 2000
An ultra-high-density high-speed loadless four-transistor SRAM macro with a dual-layered twisted bit-line and a triple-well shield.
Proceedings of the IEEE 2000 Custom Integrated Circuits Conference, 2000