Sachio Naito

According to our database, Sachio Naito authored at least 8 papers between 1969 and 1995.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of five.

1995

A Method of Current Testing for CMOS Digital and Mixed-Signal LSIs.

Yukiya Miura, Sachio Naito

IEICE Trans. Inf. Syst., 1995

1994

A fault-tolerant parallel processor modeled by a two-dimensional linear cellular automaton.

Masataka Kawanaka, Masahiro Tsunoyama, Sachio Naito

Syst. Comput. Jpn., 1994

A Case Study of Mixed-Signal Integrated Circuit Testing: An Application of Current Testing Using the Upper Limit and the Lower Limit.

Yukiya Miura, Sachio Naito, Kozo Kinoshita

Proceedings of the 1994 IEEE International Symposium on Circuits and Systems, ISCAS 1994, London, England, UK, May 30, 1994

1991

A Fault-Tolerant FFT Processor.

Masahiro Tsunoyama, Sachio Naito

Proceedings of the 1991 International Symposium on Fault-Tolerant Computing, 1991

1988

A fault-tolerant parallel processor modeled by a linear cellular automaton.

Masahiro Tsunoyama, Sachio Naito

Proceedings of the Eighteenth International Symposium on Fault-Tolerant Computing, 1988

1987

Polytonic fault-free combinational circuits for alternate-data-retry.

Sachio Naito, Osamu Fujinawa

Syst. Comput. Jpn., 1987

1972

An application of cellular logic for high speed decoding of minimum-redundancy codes.

Kenji Ohmori, Sachio Naito, T. Nanya, Koji Nezu

Proceedings of the American Federation of Information Processing Societies: Proceedings of the AFIPS '72 Fall Joint Computer Conference, December 5-7, 1972, Anaheim, California, USA, 1972

1969

Economical display generation of a large character set.

Koji Nezu, Sachio Naito

Proceedings of the American Federation of Information Processing Societies: Proceedings of the AFIPS '69 Fall Joint Computer Conference, 1969