Sachin Maheshwari
Orcid: 0000-0002-9192-2961
According to our database1,
Sachin Maheshwari
authored at least 24 papers
between 2007 and 2023.
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Bibliography
2023
Proceedings of the 21st IEEE Interregional NEWCAS Conference, 2023
2022
An Adiabatic Capacitive Artificial Neuron With RRAM-Based Threshold Detection for Energy-Efficient Neuromorphic Computing.
IEEE Trans. Circuits Syst. I Regul. Pap., 2022
Proceedings of the IEEE International Symposium on Circuits and Systems, 2022
2021
Design Flow for Hybrid CMOS/Memristor Systems - Part II: Circuit Schematics and Layout.
IEEE Trans. Circuits Syst. I Regul. Pap., 2021
Design Flow for Hybrid CMOS/Memristor Systems - Part I: Modeling and Verification Steps.
IEEE Trans. Circuits Syst. I Regul. Pap., 2021
A VHDL-Based Modeling Approach for Rapid Functional Simulation and Verification of Adiabatic Circuits.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2021
Int. J. Circuit Theory Appl., 2021
Proceedings of the IEEE International Symposium on Circuits and Systems, 2021
2020
Optimal design of flux for submerged arc weld properties based on RSM coupled with GRA and PCA.
Int. J. Manuf. Technol. Manag., 2020
CoRR, 2020
2019
Modelling, simulation and verification of 4-phase adiabatic logic design: A VHDL-Based approach.
Integr., 2019
Proceedings of the 15th Conference on Ph.D. Research in Microelectronics and Electronics, 2019
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2019
2018
Energy efficient implementation of multi-phase quasi-adiabatic Cyclic Redundancy Check in near field communication.
Integr., 2018
VHDL-Based Modelling Approach for the Digital Simulation of 4-Phase Adiabatic Logic Design.
Proceedings of the 28th International Symposium on Power and Timing Modeling, 2018
2017
Adiabatic flip-flops and sequential circuit design using novel resettable adiabatic buffers.
Proceedings of the 2017 European Conference on Circuit Theory and Design, 2017
2014
Proceedings of the 2014 International Conference on Advances in Computing, 2014
2013
Performance Analysis of Subthreshold 32-Bit Kogge-Stone Adder for Worst-Case-Delay and Power in Sub-micron Technology.
Proceedings of the VLSI Design and Test, 17th International Symposium, 2013
Convex Optimization of Energy and Delay Using Logical Effort Method in Deep Sub-micron Technology.
Proceedings of the VLSI Design and Test, 17th International Symposium, 2013
Proceedings of the VLSI Design and Test, 17th International Symposium, 2013
2011
Proceedings of the Soft Computing Models in Industrial and Environmental Applications, 2011
2010
Experimental results and analysis for Electrical Discharge Machining (EDM) of aluminium metal matrix composites with powder-mixed dielectric: Lenth's method.
Int. J. Manuf. Technol. Manag., 2010
2007
Optimisation of multiperformance characteristics in electric discharge machining of Aluminium Matrix Composites (AMCs) using Taguchi DOE methodology.
Int. J. Manuf. Res., 2007