Sabyasachee Banerjee

According to our database, Sabyasachee Banerjee authored at least 15 papers between 2012 and 2024.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2024

Power-aware partitioning and test time reduction for 3D-SoC.

Sabyasachee Banerjee, Subhashis Majumder, Bhargab B. Bhattacharya, Debesh K. Das

Innov. Syst. Softw. Eng., September, 2024

On Managing Test-Time, Power, and Layer Assignment in 3D SoCs with Built-In-Self-Repair Modules.

Sabyasachee Banerjee, Subhashis Majumder, Bhargab B. Bhattacharya

Proceedings of the 37th International Conference on VLSI Design and 23rd International Conference on Embedded Systems, 2024

2021

Designing balanced wrapper chains in 3D SoC under constrained TSVs.

Sabyasachee Banerjee, Soumendu Ghorui, Subhashis Majumder

Innov. Syst. Softw. Eng., 2021

Fast algorithms for test optimization of core based 3D SoC.

Sabyasachee Banerjee, Subhashis Majumder, Debesh K. Das, Bhargab B. Bhattacharya

Integr., 2021

2020

Experimental result of our BISR work.

Sabyasachee Banerjee

Dataset, October, 2020

2019

A Deterministic Multi-layered Partitioning Tool for Wire-Length Reduction of Monolithic 3D-IC.

Soumendu Ghorui, Sabyasachee Banerjee, Subhashis Majumder

Proceedings of the 26th IEEE International Conference on High Performance Computing, 2019

2018

Test-Time Reduction for Power-Aware 3D-SoC.

Sabyasachee Banerjee, Subhashis Majumder, Bhargab B. Bhattacharya

Proceedings of the 31st International Conference on VLSI Design and 17th International Conference on Embedded Systems, 2018

2017

A placement optimization technique for 3D IC.

Sabyasachee Banerjee, Subhashis Majumder, Abhishek Varma, Debesh K. Das

Proceedings of the 7th International Symposium on Embedded Computing and System Design, 2017

2016

Power-aware test optimization for core-based 3D-SOCs under TSV-constraints.

Sabyasachee Banerjee, Subhashis Majumder, Bhargab B. Bhattacharya

Proceedings of the 2016 IFIP/IEEE International Conference on Very Large Scale Integration, 2016

2015

Partitioning-based test time reduction for core-based 3DICs.

Sabyasachee Banerjee, Subhashis Majumder, Debesh K. Das

Proceedings of the 19th International Symposium on VLSI Design and Test, 2015

2014

A thermal aware 3D IC partitioning technique.

Sabyasachee Banerjee, Subhashis Majumder

Proceedings of the 18th International Symposium on VLSI Design and Test, 2014

A Graph-Based 3D IC Partitioning Technique.

Sabyasachee Banerjee, Subhashis Majumder, Bhargab B. Bhattacharya

Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2014

Image steganography by closest pixel-pair mapping.

Adnaan Ahmed, Nitesh Agarwal, Sabyasachee Banerjee

Proceedings of the 2014 International Conference on Advances in Computing, 2014

2012

Speed Optimization In Unplanned Traffic Using Bio-Inspired Computing And Population Knowledge Base

Prasun Ghosal, Arijit Chakraborty, Sabyasachee Banerjee, Satabdi Barman

CoRR, 2012

Honey Bee Based Vehicular Traffic Optimization and Management.

Prasun Ghosal, Arijit Chakraborty, Sabyasachee Banerjee

Proceedings of Seventh International Conference on Bio-Inspired Computing: Theories and Applications (BIC-TA 2012), 2012