S. Turgis

According to our database, S. Turgis authored at least 5 papers between 1994 and 1998.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

1998

A novel macromodel for power estimation in CMOS structures.

S. Turgis, Daniel Auvergne

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1998

1997

Internal power modelling and minimization in CMOS inverters.

S. Turgis, Jean Michel Daga, Josep M. Portal, Daniel Auvergne

Proceedings of the European Design and Test Conference, 1997

1996

Design and selection of buffers for minimum power-delay product.

S. Turgis, Nadine Azémard, Daniel Auvergne

Proceedings of the 1996 European Design and Test Conference, 1996

1995

Explicit evaluation of short circuit power dissipation for CMOS logic structures.

S. Turgis, Nadine Azémard, Daniel Auvergne

Proceedings of the 1995 International Symposium on Low Power Design 1995, 1995

1994

Design of a Real Time Geometric Classifier.

Michel Robert, Patrick Gorria, Johel Mitéran, S. Turgis

Proceedings of the EDAC - The European Conference on Design Automation, ETC - European Test Conference, EUROASIC - The European Event in ASIC Design, Proceedings, February 28, 1994