S. Sridevi Sathya Priya

Orcid: 0000-0001-9356-6721

According to our database1, S. Sridevi Sathya Priya authored at least 8 papers between 2012 and 2024.

Collaborative distances:
  • Dijkstra number2 of six.
  • Erdős number3 of five.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Dataset
Other 

Links

On csauthors.net:

Bibliography

2024
Implementation of Efficient Security Algorithm.
Proceedings of the 7th International Conference on Devices, Circuits and Systems, 2024

2023
Analysis of Various Visual Cryptographic Techniques and their Issues Based on Optimization Algorithms.
Int. J. Image Graph., November, 2023

Design of INV/BUFF Logic Locking For Enhancing the Hardware Security.
J. Electron. Test., April, 2023

2022
Design and Evaluation of XOR Arbiter Physical Unclonable Function and its Implementation on FPGA in Hardware Security Applications.
J. Electron. Test., December, 2022

2017
High Throughput AES Algorithm Using Parallel Subbytes and MixColumn.
Wirel. Pers. Commun., 2017

An Efficient Hardware Architecture for High Throughput AES Encryptor Using MUX Based Sub Pipelined S-Box.
Wirel. Pers. Commun., 2017

2015
Efficient hardware implementation of AES algorithm using bio metric key.
Int. J. Inf. Commun. Technol., 2015

2012
Survey on Efficient, Low-power, AES Image Encryption and Bio-cryptography Schemes.
Smart Comput. Rev., 2012


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