S. Sivanantham

Orcid: 0000-0002-1010-5178

Affiliations:
  • Vellore Institute of Technology, India


According to our database1, S. Sivanantham authored at least 11 papers between 2012 and 2023.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of five.

Timeline

Legend:

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PhD thesis 
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Online presence:

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Bibliography

2023
Rule precision index classifier: an associative classifier with a novel pruning measure for intrusion detection.
Pers. Ubiquitous Comput., 2023

Association Rule Mining Frequent-Pattern-Based Intrusion Detection in Network.
Comput. Syst. Sci. Eng., 2023

Optimal Test Clock Frequency Based Test Option Generation for Small Delay Defects.
IEEE Access, 2023

2022
Antenna-Multiplexer for IoMT Wireless Connectivity.
Proceedings of the 27th Asia Pacific Conference on Communications, 2022

2020
Efficient half-precision floating point multiplier targeting color space conversion.
Multim. Tools Appl., 2020

2019
High-Throughput Deblocking Filter Architecture Using Quad Parallel Edge Filter for H.264 Video Coding Systems.
IEEE Access, 2019

2018
Two-stage low power test data compression for digital VLSI circuits.
Comput. Electr. Eng., 2018

2017
Standby and dynamic power minimization using enhanced hybrid power gating structure for deep-submicron CMOS VLSI.
Microelectron. J., 2017

2014
Enhancement of test data compression with multistage encoding.
Integr., 2014

Low-power selective pattern compression for scan-based test applications.
Comput. Electr. Eng., 2014

2012
CSP-Filling: A New X-Filling Technique to Reduce Capture and Shift Power in Test Applications.
Proceedings of the International Symposium on Electronic System Design, 2012


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