S. Saqib Khursheed
Affiliations:- University of Liverpool, UK
According to our database1,
S. Saqib Khursheed
authored at least 53 papers
between 2006 and 2023.
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Bibliography
2023
IEEE Trans. Computers, July, 2023
2022
IEEE Trans. Emerg. Top. Comput., 2022
IEEE Trans. Emerg. Top. Comput., 2022
Proceedings of the IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2022
2021
IEEE Trans. Very Large Scale Integr. Syst., 2021
IC Age Estimation Methodology Using IO Pad Protection Diodes for Prevention of Recycled ICs.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2021
Proceedings of the 36th IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2021
Differential Aging Sensor to Detect Recycled ICs using Sub-threshold Leakage Current.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2021
2020
IEEE Trans. Circuits Syst., 2020
IET Comput. Digit. Tech., 2020
Proceedings of the 26th IEEE International Symposium on On-Line Testing and Robust System Design, 2020
Proceedings of the European Conference on Circuit Theory and Design, 2020
2019
A Framework for TSV Based 3D-IC to Analyze Aging and TSV Thermo-Mechanical Stress on Soft Errors.
Proceedings of the IEEE International Test Conference in Asia, 2019
Proceedings of the Security and Fault Tolerance in Internet of Things, 2019
2018
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018
Proceedings of the 23rd IEEE European Test Symposium, 2018
2017
Coarse-Grained Online Monitoring of BTI Aging by Reusing Power-Gating Infrastructure.
IEEE Trans. Very Large Scale Integr. Syst., 2017
IEEE Trans. Very Large Scale Integr. Syst., 2017
IEEE Trans. Circuits Syst. II Express Briefs, 2017
Improved Wire Length-Driven Placement Technique for Minimizing Wire Length, Area and Timing.
J. Low Power Electron., 2017
Proceedings of the IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2017
2016
IEEE Trans. Very Large Scale Integr. Syst., 2016
Co-optimization of fault tolerance, wirelength and temperature mitigation in TSV-based 3D ICs.
Proceedings of the 2016 IFIP/IEEE International Conference on Very Large Scale Integration, 2016
Proceedings of the 38th Annual International Conference of the IEEE Engineering in Medicine and Biology Society, 2016
2015
IEEE Trans. Very Large Scale Integr. Syst., 2015
DFT Architecture With Power-Distribution-Network Consideration for Delay-Based Power Gating Test.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2015
Application-specific memory protection policies for energy-efficient reliable design.
Proceedings of the 2015 International Symposium on Rapid System Prototyping, 2015
Proceedings of the 21st IEEE International On-Line Testing Symposium, 2015
Proceedings of the 20th IEEE European Test Symposium, 2015
NBTI and leakage aware sleep transistor design for reliable and energy efficient power gating.
Proceedings of the 20th IEEE European Test Symposium, 2015
2014
IEEE Trans. Very Large Scale Integr. Syst., 2014
Efficient Variation-Aware Delay Fault Simulation Methodology for Resistive Open and Bridge Defects.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2014
Proceedings of the 23rd IEEE Asian Test Symposium, 2014
2013
Improved State Integrity of Flip-Flops for Voltage Scaled Retention Under PVT Variation.
IEEE Trans. Circuits Syst. I Regul. Pap., 2013
Impact of PVT variation on delay test of resistive open and resistive bridge defects.
Proceedings of the 2013 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2013
2011
A Fast and Accurate Process Variation-Aware Modeling Technique for Resistive Bridge Defects.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2011
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2011
Proceedings of the 16th European Test Symposium, 2011
Analysis of Resistive Bridge Defect Delay Behavior in the Presence of Process Variation.
Proceedings of the 20th IEEE Asian Test Symposium, 2011
Proceedings of the 20th IEEE Asian Test Symposium, 2011
2010
Gate-Sizing-Based Single V<sub>dd</sub> Test for Bridge Defects in Multivoltage Designs.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2010
Proceedings of the 2011 IEEE International Test Conference, 2010
Proceedings of the Design, Automation and Test in Europe, 2010
2009
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2009
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2009
Test cost reduction for multiple-voltage designs with bridge defects through Gate-Sizing.
Proceedings of the Design, Automation and Test in Europe, 2009
2008
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2008
Proceedings of the 13th European Test Symposium, 2008
2007
Efficient test compaction for combinational circuits based on Fault detection count-directed clustering.
IET Comput. Digit. Tech., 2007
Proceedings of the 16th Asian Test Symposium, 2007
2006
Efficient Static Compaction Techniques for Sequential Circuits Based on Reverse-Order Restoration and Test Relaxation.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2006