S. M. Yasser Sherazi

According to our database, S. M. Yasser Sherazi authored at least 15 papers between 2010 and 2015.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2015

Low Power Analog and Digital (7, 5) Convolutional Decoders in 65 nm CMOS.

Reza Meraji, S. M. Yasser Sherazi, John B. Anderson, Henrik Sjöland, Viktor Öwall

IEEE Trans. Circuits Syst. I Regul. Pap., 2015

2014

Ultra low power transceivers for wireless sensors and body area networks.

Henrik Sjöland, John B. Anderson, Carl Bryant, Rohit Chandra, Ove Edfors, Anders J. Johansson, Nafiseh Seyed Mazloum, Reza Meraji, Peter Nilsson, Dejan Radjen, Joachim Neves Rodrigues, S. M. Yasser Sherazi, Viktor Öwall

Proceedings of the 8th International Symposium on Medical Information and Communication Technology, 2014

A digital baseband for low power FSK based receiver in 65 nm CMOS.

S. M. Yasser Sherazi, Henrik Sjöland, Peter Nilsson

Proceedings of the 21st IEEE International Conference on Electronics, Circuits and Systems, 2014

Supply-voltage down conversion for digital CMOS designs.

Peter Nilsson, Mohammed Azher Ali, Manivannan Ethiraj, S. M. Yasser Sherazi

Proceedings of the 21st IEEE International Conference on Electronics, Circuits and Systems, 2014

2013

Ultra low energy design exploration of digital decimation filters in 65 nm dual-V_T CMOS in the sub-V_T domain.

S. M. Yasser Sherazi, Joachim Neves Rodrigues, Omer Can Akgun, Henrik Sjöland, Peter Nilsson

Microprocess. Microsystems, 2013

Analog and digital approaches for an energy efficient low complexity channel decoder.

Reza Meraji, S. M. Yasser Sherazi, John B. Anderson, Henrik Sjöland, Viktor Öwall

Proceedings of the 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), 2013

Power savings in digital filters for wireless communication.

Peter Nilsson, Anusha Gundarapu, S. M. Yasser Sherazi

Proceedings of the 21st European Conference on Circuit Theory and Design, 2013

2012

A Receiver Architecture for Devices in Wireless Body Area Networks.

Henrik Sjöland, John B. Anderson, Carl Bryant, Rohit Chandra, Ove Edfors, Anders J. Johansson, Nafiseh Seyed Mazloum, Reza Meraji, Peter Nilsson, Dejan Radjen, Joachim Neves Rodrigues, S. M. Yasser Sherazi, Viktor Öwall

IEEE J. Emerg. Sel. Topics Circuits Syst., 2012

A 100-fJ/cycle sub-VT decimation filter chain in 65 nm CMOS.

S. M. Yasser Sherazi, Peter Nilsson, Henrik Sjöland, Joachim Neves Rodrigues

Proceedings of the 19th IEEE International Conference on Electronics, Circuits and Systems, 2012

A 500 fW/bit 14 fJ/bit-access 4kb standard-cell based sub-VT memory in 65nm CMOS.

Pascal Andreas Meinerzhagen, Oskar Andersson, Babak Mohammadi, S. M. Yasser Sherazi, Andreas Peter Burg, Joachim Neves Rodrigues

Proceedings of the 38th European Solid-State Circuit conference, 2012

2011

Benchmarking of Standard-Cell Based Memories in the Sub- V_T Domain in 65-nm CMOS Technology.

Pascal Andreas Meinerzhagen, S. M. Yasser Sherazi, Andreas Peter Burg, Joachim Neves Rodrigues

IEEE J. Emerg. Sel. Topics Circuits Syst., 2011

Impact of switching activity on the energy minimum voltage for 65 nm sub-VT CMOS.

Oskar Andersson, S. M. Yasser Sherazi, Joachim Neves Rodrigues

Proceedings of the 2011 NORCHIP, Lund, Sweden, November 14-15, 2011, 2011

Design exploration of a 65 nm Sub-VT CMOS digital decimation filter chain.

S. M. Yasser Sherazi, Peter Nilsson, Omer Can Akgun, Henrik Sjöland, Joachim Neves Rodrigues

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2011), 2011

Synthesis strategies for sub-VT systems.

Pascal Andreas Meinerzhagen, Oskar Andersson, S. M. Yasser Sherazi, Andreas Peter Burg, Joachim Neves Rodrigues

Proceedings of the 20th European Conference on Circuit Theory and Design, 2011

2010

Reduction of Substrate Noise in Sub Clock Frequency Range.

S. M. Yasser Sherazi, Shahzad Asif, Erik Backenius, Mark Vesterbacka

IEEE Trans. Circuits Syst. I Regul. Pap., 2010