S. M. Rezaul Hasan
Orcid: 0000-0003-0428-3311
According to our database1,
S. M. Rezaul Hasan
authored at least 52 papers
between 1995 and 2023.
Collaborative distances:
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Bibliography
2023
A Low Phase-Lag Self-Powered SECE Interface Circuit for Pressure-Type Piezoelectric Energy-Harvesting Compatible With COTS Pressure Sensors.
IEEE Trans. Very Large Scale Integr. Syst., October, 2023
2022
A 25-30-GHz RMS Error-Minimized 360° Continuous Analog Phase Shifter Using Closed-Loop Self-Tuning I/Q Generator.
IEEE Trans. Very Large Scale Integr. Syst., 2022
Ultraviolet-C Photoresponsivity Using Fabricated TiO2 Thin Films and Transimpedance-Amplifier-Based Test Setup.
Sensors, 2022
A Process-Based Temperature Compensated On-Chip CMOS VHF VCRO in 130-nm Si-Ge BiCMOS by Implementing an Empirical Control Equation.
IEEE Access, 2022
2021
A new ASIC implementation of an advanced encryption standard (AES) crypto-hardware accelerator.
Microelectron. J., 2021
On the gm-boosted common source with source degeneration and its configuration as a transimpedance amplifier.
Int. J. Circuit Theory Appl., 2021
Int. J. Circuit Theory Appl., 2021
On the g<sub>m</sub>-Boosted Miller-Effect Minimized Inverter-Cascode Transimpedance Amplifier for Sensor Applications.
IEEE Access, 2021
2020
A Low Duty Cycle Burst-Mode Telemeter Signal Generation Technique for VHF Insect Tracking and Its CMOS Implementation.
IEEE Trans. Very Large Scale Integr. Syst., 2020
The "nonideal" drain-loaded source-follower and accurate differential-amplifier analysis.
Int. J. Circuit Theory Appl., 2020
2017
IEEE Trans. Circuits Syst. II Express Briefs, 2017
Optimized low-power CMOS active-electrode-pair for low-frequency multi-channel biomedical stimulation.
Microelectron. J., 2017
IEEE Access, 2017
2016
A VLSI Circuit Emulation of Chemical Synaptic Transmission Dynamics and Postsynaptic DNA Transcription.
IEEE Trans. Very Large Scale Integr. Syst., 2016
Quadruply Split Cross-Driven Doubly Recycled g<sub>m</sub>-Doubling Recycled Folded Cascode for Microsensor Instrumentation Amplifiers.
IEEE Trans. Circuits Syst. II Express Briefs, 2016
IEEE Trans. Circuits Syst. I Regul. Pap., 2016
Int. J. Circuit Theory Appl., 2016
IEEE Access, 2016
2013
A 0.8V 40 Gb/s Novel CMOS Regulated Cascode Trans-impedance Amplifier for Optical Sensing Applications.
J. Signal Process. Syst., 2013
Design and Performance Analysis of a 866-MHz Low-Power Optimized CMOS LNA for UHF RFID.
IEEE Trans. Ind. Electron., 2013
Integrated Circuit Modeling of Biocellular Post-Transcription Gene Mechanisms Regulated by MicroRNA and Proteasome.
IEEE Trans. Circuits Syst. I Regul. Pap., 2013
Low-power compact composite field AES S-Box/Inv S-Box design in 65 nm CMOS using Novel XOR Gate.
Integr., 2013
2012
A 3-5 GHz Current-Reuse g<sub>m</sub>-Boosted CG LNA for Ultrawideband in 130 nm CMOS.
IEEE Trans. Very Large Scale Integr. Syst., 2012
2011
Microelectron. J., 2011
2010
Analysis and Design of a Multistage CMOS Band-Pass Low-Noise Preamplifier for Ultrawideband RF Receiver.
IEEE Trans. Very Large Scale Integr. Syst., 2010
A Low-voltage Scalable (1.8 V-0.75 V) CMOS Folded-cascode LC quadrature VCO for RF Receivers.
J. Circuits Syst. Comput., 2010
A micro-sequenced CMOS model for cell signalling pathway using G-protein and phosphorylation cascade.
Int. J. Comput. Appl. Technol., 2010
Int. J. Comput. Appl. Technol., 2010
2009
A Novel Low-voltage CMOS Variable Gain amplifier with Gain-Independent Input Impedance Matching for DTV Tuning Applications.
J. Circuits Syst. Comput., 2009
A central pattern generator circuit for rhythmic robotic chewing locomotion in low-voltage analog CMOS technology.
Artif. Life Robotics, 2009
2008
A Novel Mixed-Signal Integrated Circuit Model for DNA-Protein Regulatory Genetic Circuits and Genetic State Machines.
IEEE Trans. Circuits Syst. I Regul. Pap., 2008
Analog CMOS charge model for molecular redox electron-transfer reactions and bio-chemical pathways.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2008), 2008
2007
Proceedings of the 20th International Conference on VLSI Design (VLSI Design 2007), 2007
A Bias-Controlled Noise-Canceling CMOS Tuned Low Noise Amplifier for UWB Transceivers.
Proceedings of the 14th IEEE International Conference on Electronics, 2007
2006
A Novel Current Feed-back Sub-Nano-Siemen Transconductance Circuit Suitable for Large Time-Constant Bio-medical Applications.
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems 2006, 2006
Stability and Compensation Technique for a CMOS Amperometric Potentiostat Circuit for Redox Sensors.
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems 2006, 2006
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems 2006, 2006
2005
Design of a low-power 3.5-GHz broad-band CMOS transimpedance amplifier for optical transceivers.
IEEE Trans. Circuits Syst. I Regul. Pap., 2005
Proceedings of the 5th IEEE International Workshop on System-on-Chip for Real-Time Applications (IWSOC 2005), 2005
2004
A 4GHz Low-Power Folded-Cascode CMOS LC Quadrature VCO for RF Transceivers.
Proceedings of the International Conference on Embedded Systems and Applications, 2004
2003
On the parasitic-sensitivity of switched-capacitor summing-integrator structures for ΣΔ modulators.
IEEE Trans. Circuits Syst. II Express Briefs, 2003
Proceedings of the 3rd IEEE International Workshop on System-on-Chip for Real-Time Applications (IWSOC'03), 30 June, 2003
A 5GHz CMOS voltage-current feedback wide-band transimpedance amplifier for optical transceivers.
Proceedings of the 2003 10th IEEE International Conference on Electronics, 2003
A 5GHz CMOS digitally controlled oscillator with a 3GHz tuning range for PLL applications.
Proceedings of the 2003 10th IEEE International Conference on Electronics, 2003
2002
Reduction of Power Dissipation in Dynamic BiCMOS Logic Gates by Transistor Reordering.
VLSI Design, 2002
1999
Proceedings of the 9th Great Lakes Symposium on VLSI (GLS-VLSI '99), 1999
1998
600 MHz Digitally Controlled BiCMOS Oscillator (DCO) for VLSI Signal Processing & Communication Applications.
Proceedings of the 8th Great Lakes Symposium on VLSI (GLS-VLSI '98), 1998
1997
IEEE J. Solid State Circuits, 1997
1995
Proceedings of International Conference on Neural Networks (ICNN'95), Perth, WA, Australia, November 27, 1995
Proceedings of International Conference on Neural Networks (ICNN'95), Perth, WA, Australia, November 27, 1995