S. Karen Khatamifard

Orcid: 0000-0002-7574-8975

According to our database1, S. Karen Khatamifard authored at least 22 papers between 2016 and 2022.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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On csauthors.net:

Bibliography

2022
Energy-efficient and Reliable Inference in Nonvolatile Memory under Extreme Operating Conditions.
ACM Trans. Embed. Comput. Syst., September, 2022

CRAM-Seq: Accelerating RNA-Seq Abundance Quantification Using Computational RAM.
IEEE Trans. Emerg. Top. Comput., 2022

GeNVoM: Read Mapping Near Non-Volatile Memory.
IEEE ACM Trans. Comput. Biol. Bioinform., 2022

2020
PIMBALL: Binary Neural Networks in Spintronic Memory.
ACM Trans. Archit. Code Optim., 2020

Voltage Noise Mitigation With Barrier Approximation.
IEEE Comput. Archit. Lett., 2020

MOUSE: Inference In Non-volatile Memory for Energy Harvesting Applications.
Proceedings of the 53rd Annual IEEE/ACM International Symposium on Microarchitecture, 2020

2019
Exploiting Algorithmic Noise Tolerance for Scalable On-Chip Voltage Regulation.
IEEE Trans. Very Large Scale Integr. Syst., 2019

A Machine Learning Accelerator In-Memory for Energy Harvesting.
CoRR, 2019

Barrier Synchronization vs. Voltage Noise: A Quantitative Analysis.
Proceedings of the IEEE International Symposium on Workload Characterization, 2019

POWERT Channels: A Novel Class of Covert CommunicationExploiting Power Management Vulnerabilities.
Proceedings of the 25th IEEE International Symposium on High Performance Computer Architecture, 2019

2018
On Approximate Speculative Lock Elision.
IEEE Trans. Multi Scale Comput. Syst., 2018

Approximate Communication: Techniques for Reducing Communication Bottlenecks in Large-Scale Parallel Systems.
ACM Comput. Surv., 2018

Computational RAM to Accelerate String Matching at Scale.
CoRR, 2018

Exploiting Processing in Non-Volatile Memory for Binary Neural Network Accelerators.
CoRR, 2018

A New Class of Covert Channels Exploiting Power Management Vulnerabilities.
IEEE Comput. Archit. Lett., 2018

On Memory System Design for Stochastic Computing.
IEEE Comput. Archit. Lett., 2018

Efficient In-Memory Processing Using Spintronics.
IEEE Comput. Archit. Lett., 2018

Mitigation of NBTI induced performance degradation in on-chip digital LDOs.
Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018

2017
Efficiency, Stability, and Reliability Implications of Unbalanced Current Sharing Among Distributed On-Chip Voltage Regulators.
IEEE Trans. Very Large Scale Integr. Syst., 2017

A Non-volatile Near-Memory Read Mapping Accelerator.
CoRR, 2017

ThermoGater: Thermally-Aware On-Chip Voltage Regulation.
Proceedings of the 44th Annual International Symposium on Computer Architecture, 2017

2016
VARIUS-TC: A modular architecture-level model of parametric variation for thin-channel switches.
Proceedings of the 34th IEEE International Conference on Computer Design, 2016


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