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S. K. Patnaik

According to our database1, S. K. Patnaik authored at least 5 papers between 2008 and 2019.

Collaborative distances:
  • Dijkstra number2 of six.
  • Erdős number3 of five.

Timeline

2008
2010
2012
2014
2016
2018
0
1
2
3
1
1
2
1

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Dataset
Other 

Links

On csauthors.net:

Bibliography

2019
A dsPIC based optimal sizing of solar PV plant using ultra capacitors for transient power delivery.
[BibTeX]
[DOI]
K. Karthikeyan
,
S. K. Patnaik
,
Manickam Baskar
,
E. Jeyashree
Microprocess. Microsystems, 2019

2013
Design and Implementation of a Novel Control Architecture by Combining H<sub>∞</sub> and sliding Mode Schemes for a Boost Converter.
[BibTeX]
[DOI]
Shama Ravichandran
,
K. S. Nagaraj
,
S. K. Patnaik
J. Circuits Syst. Comput., 2013

2009
A Non-Iterative Controller Design for a BLDC Drive System.
[BibTeX]
[DOI]
C. Ganesh
,
Jeba Sankar
,
Saranya Ramakrishnan
,
Geethu S. Nair
,
S. K. Patnaik
Proceedings of the ARTCom 2009, 2009

2008
H<sub>infinity</sub> Loop-Shaping Controller for a Boost converter with Harmonic Reduction.
[BibTeX]
[DOI]
S. K. Patnaik
,
B. Umamaheswari
J. Circuits Syst. Comput., 2008

A heuristic approach to robust control design for boost power converters with harmonic reduction.
[BibTeX]
[DOI]
S. K. Patnaik
,
B. Umamaheswari
Int. J. Autom. Control., 2008


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