S. Gurunarayanan
Orcid: 0000-0001-5596-4964Affiliations:
- Birla Institute of Technology and Science Pilani, Rajasthan, India
According to our database1,
S. Gurunarayanan
authored at least 23 papers
between 2006 and 2024.
Collaborative distances:
Collaborative distances:
Timeline
Legend:
Book In proceedings Article PhD thesis Dataset OtherLinks
Online presence:
-
on orcid.org
On csauthors.net:
Bibliography
2024
Circuits Syst. Signal Process., July, 2024
2022
Design of a Programmable Delay Line with On-Chip Calibration to Achieve Immunity Against Process Variations.
Proceedings of the VLSI Design and Test - 26th International Symposium, 2022
2021
Design of an MTJ/CMOS-Based Asynchronous System for Ultra-Low Power Energy Autonomous Applications.
J. Circuits Syst. Comput., 2021
2020
An optimal delay aware task assignment scheme for wireless SDN networked edge cloudlets.
Future Gener. Comput. Syst., 2020
Proceedings of the 2020 24th International Symposium on VLSI Design and Test (VDAT), 2020
2019
IEEE Wirel. Commun. Lett., 2019
A testbed validated simple time synchronization protocol for clustered wireless sensor networks for IoT.
J. Intell. Fuzzy Syst., 2019
A low power high speed MTJ based non-volatile SRAM cell for energy harvesting based IoT applications.
Integr., 2019
2017
J. King Saud Univ. Comput. Inf. Sci., 2017
2015
An adaptive migration-replication scheme (AMR) for shared cache in chip multiprocessors.
J. Supercomput., 2015
Microprocess. Microsystems, 2015
An FPGA-Based Architecture for Local Similarity Measure for Image/Video Processing Applications.
Proceedings of the 28th International Conference on VLSI Design, 2015
An embedded framework for accurate object localization using center of gravity measure with mean shift procedure.
Proceedings of the 19th International Symposium on VLSI Design and Test, 2015
2014
A Novel Architecture for FPGA Implementation of Otsu's Global Automatic Image Thresholding Algorithm.
Proceedings of the 2014 27th International Conference on VLSI Design, 2014
Architectures and algorithms for image and video processing using FPGA-based platform.
Proceedings of the 18th International Symposium on VLSI Design and Test, 2014
2013
Fine grain thread scheduling on multicore processors: cores with multiple functional units.
Proceedings of the 6th ACM India Computing Convention, 2013
2012
An efficient method to compute static single assignment form for multicore architecture.
Proceedings of the 1st International Conference on Recent Advances in Information Technology, 2012
2008
Proceedings of the 2008 ACM Symposium on Applied Computing (SAC), 2008
2007
An Energy Efficient Selective Placement Scheme for Set-Associative Data Cache in Embedded System.
Proceedings of the 2007 International Conference on Embedded Systems & Applications, 2007
EFFS: Efficient Flash File System for Wireless Sensor Nodes.
Proceedings of the 2007 International Conference on Embedded Systems & Applications, 2007
2006
Variants of Priority Scheduling Algorithms for Reducing Context-Switches in Real-Time Systems.
Proceedings of the Distributed Computing and Networking, 8th International Conference, 2006
Proceedings of the Advances in Computer Systems Architecture, 11th Asia-Pacific Conference, 2006