S. Deepanjali

Orcid: 0009-0007-8740-5084

According to our database1, S. Deepanjali authored at least 7 papers between 2021 and 2024.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of five.

Timeline

Legend:

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In proceedings 
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PhD thesis 
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Links

On csauthors.net:

Bibliography

2024
A twofold bio-inspired system for mitigating SEUs in the controllers of digital system deployed on FPGA.
J. Supercomput., May, 2024

Scalable and Accelerated Self-healing Control Circuit Using Evolvable Hardware.
ACM Trans. Design Autom. Electr. Syst., March, 2024

Evolvable Hardware for Fault Mitigation in Control Circuits.
Proceedings of the 37th International Conference on VLSI Design and 23rd International Conference on Embedded Systems, 2024

Fault Resilient Micro-Coded Control Unit for Space-Based Digital Systems.
Proceedings of the 28th International Symposium on VLSI Design and Test, 2024

2022
Self Healing Controllers to Mitigate SEU in the Control Path of FPGA Based System: A Complete Intrinsic Evolutionary Approach.
J. Electron. Test., 2022

Fault Tolerant Technique for Processor Control Path to Mitigate SEUs in FPGA.
Proceedings of the IEEE International Symposium on Smart Electronic Systems, 2022

2021
Automatic Face Mask Detection Using a Hide and Seek Algorithm.
Proceedings of the Progress in Pattern Recognition, Image Analysis, Computer Vision, and Applications, 2021


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