S. Biesemans

According to our database, S. Biesemans authored at least 6 papers between 2007 and 2024.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2024

Monolithic Complementary Field Effect Transistors (CFET) Demonstrated using Middle Dielectric Isolation and Stacked Contacts.

Steven Demuynck, Victor Vega-Gonzalez, C. Toledo de Carvalho Cavalcante, L. Petersen Barbosa Lima, K. Stiers, C. Sheng, A. Vandooren, M. Hosseini, X. Zhou, Hans Mertens, Thomas Chiarella, Jürgen Bömmels, Roger Loo, E. Rosseel, Clement Porret, Y. Shimura, A. Akula, G. Mannaert, S. Choudhury, V. Brissonneau, E. Dupuy, T. Sarkar, Nathali Franchina-Vergel, A. Peter, Nicolas Jourdan, J. P. Soulie, Kevin Vandersmissen, F. Sebaai, P. Puttarame Gowda, K. Lai, A. Mingardi, S. Sumar Sarkar, K. D'Have, B. T. Chan, A. Sepulveda Marquez, R. Langer, I. Gyo Koo, E. Altamirano Sanchez, Katia Devriendt, P. Rincon Delgadillo, F. Lazzarino, Jérôme Mitard, J. Geypen, E. Grieten, D. Batuk, Y.-F. Chen, F. Verbeek, F. Holsteyns, S. Subramanian, N. Horiguchi, S. Biesemans

Proceedings of the IEEE Symposium on VLSI Technology and Circuits 2024, 2024

Vt Fine-Tuning in Multi-Vt Gate-All-Around Nanosheet nFETs Using Rare-Earth Oxide-Based Dipole-First Gate Stack Compatible with CFET Integration.

Hiroaki Arimura, Hans Mertens, Jacopo Franco, L. Lukose, W. Maqsood, S. Brus, Thomas Chiarella, A. Impagnatiello, S. Homkar, V. K. Mootheri, C. Yin, G. Alessio Verni, M. Givens, L. Petersen Barbosa Lima, S. Biesemans, N. Horiguchi

Proceedings of the IEEE Symposium on VLSI Technology and Circuits 2024, 2024

2023

Integration of a Stacked Contact MOL for Monolithic CFET.

Victor Vega-Gonzalez, D. Radisic, Bt Chan, S. Choudhury, S. Wang, A. Mingardi, Q. Toan Le, H. Decoster, Yusuke Oniki, P. Puttarame, Kevin Vandersmissen, J. P. Soulie, A. Peter, A. Sepulveda, D. Batuk, G. T. Martinez, Olivier Richard, Jürgen Bömmels, S. Biesemans, E. Dentoni Litta, Naoto Horiguchi, Seongho Park, Zsolt Tokei

Proceedings of the 2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits), 2023

Nanosheet-based Complementary Field-Effect Transistors (CFETs) at 48nm Gate Pitch, and Middle Dielectric Isolation to enable CFET Inner Spacer Formation and Multi-Vt Patterning.

Hans Mertens, M. Hosseini, Thomas Chiarella, D. Zhou, S. Wang, G. Mannaert, E. Dupuy, D. Radisic, Z. Tao, Yusuke Oniki, Andriy Hikavyy, R. Rosseel, A. Mingardi, S. Choudhury, P. Puttarame Gowda, F. Sebaai, A. Peter, Kevin Vandersmissen, J. P. Soulie, An De Keersgieter, L. Petersen Barbosa Lima, C. Cavalcante, D. Batuk, G. T. Martinez, J. Geypen, F. Seidel, K. Paulussen, P. Favia, Jürgen Bömmels, Roger Loo, P. Wong, A. Sepulveda Marquez, B. T. Chan, Jérôme Mitard, S. Subramanian, S. Demuynck, E. Dentoni Litta, N. Horiguchi, S. Samavedam, S. Biesemans

Proceedings of the 2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits), 2023

2009

Migrating from planar to FinFET for further CMOS scaling: SOI or bulk?

Thomas Chiarella, Liesbeth Witters, Abdelkarim Mercha, Christoph Kerner, Rok Dittrich, Michal Rakowski, Claude Ortolland, Lars-Åke Ragnarsson, Bertrand Parvais, An De Keersgieter, Stefan Kubicek, Augusto Redolfi, R. Rooyackers, C. Vrancken, S. Brus, A. Lauwers, Philippe Absil, S. Biesemans, Thomas Y. Hoffmann

Proceedings of the 35th European Solid-State Circuits Conference, 2009

2007

Optimization of HfSiON using a design of experiment (DOE) approach on 0.45 V V_t Ni-FUSI CMOS transistors.

A. Rothschild, R. Mitsuhashi, Christoph Kerner, X. Shi, J. L. Everaert, L. Date, Thierry Conard, Olivier Richard, C. Vrancken, R. Verbeeck, Anabela Veloso, A. Lauwers, Muriel de Potter de ten Broeck, I. Debusschere, M. Jurczak, M. Niwa, Philippe Absil, S. Biesemans

Microelectron. Reliab., 2007