S. Balamurugan

According to our database, S. Balamurugan authored at least 11 papers between 2012 and 2023.

Collaborative distances:

• Dijkstra number of six.
• Erdős number of five.

2023

Design, prototype validation, and reliability analysis of a multi-input DC/DC converter for grid-independent hybrid electric vehicles.

Saikumar Bairabathina, S. Balamurugan

Int. J. Circuit Theory Appl., May, 2023

Leveraging GaN for DC-DC Power Modules for Efficient EVs: A Review.

Paramanand Prajapati, S. Balamurugan

IEEE Access, 2023

2022

HealthSaver: a neural network based hospital recommendation system framework on flask webapplication with realtime database and RFID based attendance system.

Aakash Choudhury, Arjav Choudhury, Umashankar Subramanium, S. Balamurugan

J. Ambient Intell. Humaniz. Comput., 2022

2019

Modern security threats in the Internet of Things (IoT): Attacks and Countermeasures.

Gowthamaraj Rajendran, R. S. Ragul Nivash, Purushotham Parthiban Parthy, S. Balamurugan

Proceedings of the 2019 International Carnahan Conference on Security Technology, 2019

2018

Design of 5-3 multicolumn compressor for high performance multiplier.

R. Marimuthu, S. Balamurugan, Partha Sharathi Mallick

Int. J. Comput. Aided Eng. Technol., 2018

Design of High Speed 5: 2 and 7: 2 Compressor Using Nanomagnetic Logic.

Shantanu Agarwal, G. Harish, S. Balamurugan, R. Marimuthu

Proceedings of the VLSI Design and Test - 22nd International Symposium, 2018

Realization of 2-D DCT Using Adder Compressor.

Raunak R. Lahoti, Shantanu Agarwal, S. Balamurugan, R. Marimuthu

Proceedings of the Soft Computing for Problem Solving, 2018

Design and Analysis of 4-Bit Squarer Circuit Using Minority and Majority Logic in MagCAD.

Saurabh Kumar, R. Marimuthu, S. Balamurugan

Proceedings of the Soft Computing for Problem Solving, 2018

2017

Error Compensation Techniques for Fixed-Width Array Multiplier Design - A Technical Survey.

S. Balamurugan, Partha Sharathi Mallick

J. Circuits Syst. Comput., 2017

2012

Design of low power fixed-width multiplier with row bypassing.

S. Balamurugan, Sneha Ghosh, Atul, Balakumaran Srirangaswamy, R. Marimuthu, Partha Sharathi Mallick

IEICE Electron. Express, 2012

FPGA design and implementation of truncated multipliers using bypassing technique.

S. Balamurugan, Balakumaran Srirangaswamy, R. Marimuthu, Partha Sharathi Mallick

Proceedings of the 2012 International Conference on Advances in Computing, 2012