S. Arash Mirhaj

According to our database, S. Arash Mirhaj authored at least 5 papers between 2008 and 2022.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2022

Automated Design of Analog Circuits Using Reinforcement Learning.

Keertana Settaluri, Zhaokai Liu, Rishubh Khurana, Arash Mirhaj, Rajeev Jain, Borivoje Nikolic

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022

2015

14.9 Sub-sampling all-digital fractional-N frequency synthesizer with -111dBc/Hz in-band phase noise and an FOM of -242dB.

Zuow-Zun Chen, Yen-Hsiang Wang, Jaewook Shin, Yan Zhao, Seyed Arash Mirhaj, Yen-Cheng Kuan, Huan-Neng Ron Chen, Chewnpu Jou, Ming-Hsien Tsai, Fu-Lung Hsueh, Mau-Chung Frank Chang

Proceedings of the 2015 IEEE International Solid-State Circuits Conference, 2015

2011

High speed sample and hold design using closed-loop pole-zero cancelation.

S. Arash Mirhaj, Arashk Norouzpour-Shirazi, Shahin Jafarabadi-Ashtiani, Omid Shoaei

Microelectron. J., 2011

Linearity improvement of open-loop NMOS source-follower sample and hold circuits.

Arashk Norouzpour-Shirazi, S. Arash Mirhaj, Shahin Jafarabadi-Ashtiani, Omid Shoaei

IET Circuits Devices Syst., 2011

2008

A Novel Low Power 1 GS/s S&H Architecture With Improved Analog Bandwidth.

Arashk Norouzpour-Shirazi, S. Arash Mirhaj, Shahin Jafarabadi-Ashtiani, Omid Shoaei

IEEE Trans. Circuits Syst. II Express Briefs, 2008