Ryuta Kawano

According to our database, Ryuta Kawano authored at least 17 papers between 2015 and 2022.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of three.

2022

A traffic-aware memory-cube network using bypassing.

Yoshiya Shikama, Ryuta Kawano, Hiroki Matsutani, Hideharu Amano, Yusuke Nagasaka, Naoto Fukumoto, Michihiro Koibuchi

Microprocess. Microsystems, April, 2022

Dynamic Routing Reconfiguration for Low-Latency and Deadlock-Free Interconnection Networks.

Ryuta Kawano, Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano

Proceedings of the Tenth International Symposium on Computing and Networking, 2022

2021

Low-Latency Low-Energy Memory-Cube Networks using Dual-Voltage Datapaths.

Yoshiya Shikama, Ryuta Kawano, Hiroki Matsutani, Hideharu Amano, Yusuke Nagasaka, Naoto Fukumoto, Michihiro Koibuchi

Proceedings of the 29th Euromicro International Conference on Parallel, 2021

GPU Parallelization of All-Pairs-Shortest-Path Algorithm in Low-Degree Unweighted Regular Graph.

Ryuta Kawano, Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano

Proceedings of the ACIT 2021: The 8th International Virtual Conference on Applied Computing & Information Technology, Kanazawa, Japan, June 20, 2021

2020

Traffic-Independent Multi-Path Routing for High-Throughput Data Center Networks.

Ryuta Kawano, Ryota Yasudo, Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano

IEICE Trans. Inf. Syst., 2020

A Generalized Theory Based on the Turn Model for Deadlock-Free Irregular Networks.

Ryuta Kawano, Ryota Yasudo, Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano

IEICE Trans. Inf. Syst., 2020

Layout-Oriented Low-Diameter Topology for HPC Interconnection Networks.

Ryuta Kawano, Hiroki Matsutani, Hideharu Amano

Proceedings of the Eighth International Symposium on Computing and Networking Workshops, 2020

2019

Deadlock-Free Layered Routing for Infiniband Networks.

Ryuta Kawano, Hiroki Matsutani, Hideharu Amano

Proceedings of the Seventh International Symposium on Computing and Networking Workshops, 2019

2018

k-Optimized Path Routing for High-Throughput Data Center Networks.

Ryuta Kawano, Ryota Yasudo, Hiroki Matsutani, Hideharu Amano

Proceedings of the Sixth International Symposium on Computing and Networking, 2018

2017

Body Bias Domain Partitioning Size Exploration for a Coarse Grained Reconfigurable Accelerator.

Yusuke Matsushita, Hayate Okuhara, Koichiro Masuyama, Yu Fujita, Ryuta Kawano, Hideharu Amano

IEICE Trans. Inf. Syst., 2017

A Novel Channel Assignment Method to Ensure Deadlock-Freedom for Deterministic Routing.

Ryuta Kawano, Hiroshi Nakahara, Seiichi Tade, Ikki Fujiwara, Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano

IEICE Trans. Inf. Syst., 2017

A Layout-Oriented Routing Method for Low-Latency HPC Networks.

Ryuta Kawano, Hiroshi Nakahara, Ikki Fujiwara, Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano

IEICE Trans. Inf. Syst., 2017

HiRy: An Advanced Theory on Design of Deadlock-Free Adaptive Routing for Arbitrary Topologies.

Ryuta Kawano, Ryota Yasudo, Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano

Proceedings of the 23rd IEEE International Conference on Parallel and Distributed Systems, 2017

2016

LOREN: A Scalable Routing Method for Layout-Conscious Random Topologies.

Ryuta Kawano, Hiroshi Nakahara, Ikki Fujiwara, Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano

Proceedings of the Fourth International Symposium on Computing and Networking, 2016

Body bias grain size exploration for a coarse grained reconfigurable accelerator.

Yusuke Matsushita, Hayate Okuhara, Koichiro Masuyama, Yu Fujita, Ryuta Kawano, Hideharu Amano

Proceedings of the 26th International Conference on Field Programmable Logic and Applications, 2016

ACRO: Assignment of channels in reverse order to make arbitrary routing deadlock-free.

Ryuta Kawano, Hiroshi Nakahara, Seiichi Tade, Ikki Fujiwara, Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano

Proceedings of the 15th IEEE/ACIS International Conference on Computer and Information Science, 2016

2015

Optimized Core-Links for Low-Latency NoCs.

Ryuta Kawano, Seiichi Tade, Ikki Fujiwara, Hiroki Matsutani, Hideharu Amano, Michihiro Koibuchi

Proceedings of the 23rd Euromicro International Conference on Parallel, 2015