Ryusuke Egawa

Proceedings of the Sixth International Symposium on Computing and Networking, 2018

An energy-aware set-level refreshing mechanism for eDRAM last-level caches.

[BibT_eX]

[DOI]

Proceedings of the 2018 IEEE Symposium in Low-Power and High-Speed Chips, 2018

A Failure Prediction-Based Adaptive Checkpointing Method with Less Reliance on Temperature Monitoring for HPC Applications.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Conference on Cluster Computing, 2018

Automatic Hyperparameter Tuning of Machine Learning Models under Time Constraints.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Conference on Big Data (IEEE BigData 2018), 2018

2017

Potential of a modern vector supercomputer for practical applications: performance evaluation of SX-ACE.

[BibT_eX]

[DOI]

J. Supercomput., 2017

A Directive Generation Approach to High Code-Maintainability for Various HPC Systems.

[BibT_eX]

[DOI]

Int. J. Netw. Comput., 2017

An Application-Level Incremental Checkpointing Mechanism with Automatic Parameter Tuning.

[BibT_eX]

[DOI]

Kazuhiko Komatsu

Proceedings of the Fifth International Symposium on Computing and Networking, 2017

Designing an Open Database of System-Aware Code Optimizations.

[BibT_eX]

[DOI]

Kazuhiko Komatsu

Proceedings of the Fifth International Symposium on Computing and Networking, 2017

A Memory Congestion-Aware MPI Process Placement for Modern NUMA Systems.

[BibT_eX]

[DOI]

Mulya Agung

Kazuhiko Komatsu

Proceedings of the 24th IEEE International Conference on High Performance Computing, 2017

An Adaptive Demotion Policy for High-Associativity Caches.

[BibT_eX]

[DOI]

Masayuki Sato

Proceedings of the 8th International Symposium on Highly Efficient Accelerators and Reconfigurable Technologies, 2017

An application-adaptive data allocation method for multi-channel memory.

[BibT_eX]

[DOI]

Proceedings of the 2017 IEEE Symposium in Low-Power and High-Speed Chips, 2017

An Adjacent-Line-Merging Writeback Scheme for STT-RAM last-level caches.

[BibT_eX]

[DOI]

Proceedings of the 2017 IEEE Symposium in Low-Power and High-Speed Chips, 2017

Vectorization-Aware Loop Optimization with User-Defined Code Transformations.

[BibT_eX]

[DOI]

Proceedings of the 2017 IEEE International Conference on Cluster Computing, 2017

Performance and Power Analysis of SX-ACE Using HP-X Benchmark Programs.

[BibT_eX]

[DOI]

Proceedings of the 2017 IEEE International Conference on Cluster Computing, 2017

2016

Effects of Stacking Granularity on 3-D Stacked Floating-point Fused Multiply Add Units.

[BibT_eX]

[DOI]

SIGARCH Comput. Archit. News, 2016

A Memory-Efficient Implementation of a Plasmonics Simulation Application on SX-ACE.

[BibT_eX]

[DOI]

Int. J. Netw. Comput., 2016

Translation of Large-Scale Simulation Codes for an OpenACC Platform Using the Xevolver Framework.

[BibT_eX]

[DOI]

Int. J. Netw. Comput., 2016

A Directive Generation Approach Using User-Defined Rules.

[BibT_eX]

[DOI]

Proceedings of the Fourth International Symposium on Computing and Networking, 2016

A cache partitioning mechanism to protect shared data for CMPs.

[BibT_eX]

[DOI]

Proceedings of the 2016 IEEE Symposium in Low-Power and High-Speed Chips, 2016

A power-aware LLC control mechanism for the 3D-stacked memory system.

[BibT_eX]

[DOI]

Proceedings of the 2016 IEEE International 3D Systems Integration Conference, 2016

2015

FLEXII: A Flexible Insertion Policy for Dynamic Cache Resizing Mechanisms.

[BibT_eX]

[DOI]

IEICE Trans. Electron., 2015

A Case Study of Memory Optimization for Migration of a Plasmonics Simulation Application to SX-ACE.

[BibT_eX]

[DOI]

Proceedings of the Third International Symposium on Computing and Networking, 2015

Migration of an Atmospheric Simulation Code to an OpenACC Platform Using the Xevolver Framework.

[BibT_eX]

[DOI]

Proceedings of the Third International Symposium on Computing and Networking, 2015

An energy-efficient dynamic memory address mapping mechanism.

[BibT_eX]

[DOI]

Proceedings of the 2015 IEEE Symposium in Low-Power and High-Speed Chips, 2015

Design of a 3-D stacked floating-point Goldschmidt divider.

[BibT_eX]

[DOI]

Hiroaki Kobayashi

Proceedings of the 2015 International 3D Systems Integration Conference, 2015

2014

MVP-Cache: A Multi-Banked Cache Memory for Energy-Efficient Vector Processing of Multimedia Applications.

[BibT_eX]

[DOI]

IEICE Trans. Inf. Syst., 2014

A Compiler-Assisted OpenMP Migration Method Based on Automatic Parallelizing Information.

[BibT_eX]

[DOI]

Proceedings of the Supercomputing - 29th International Conference, 2014

Xevolver: An XML-based code translation framework for supporting HPC application migration.

[BibT_eX]

[DOI]

Proceedings of the 21st International Conference on High Performance Computing, 2014

An energy optimization method for vector processing mechanisms.

[BibT_eX]

[DOI]

Proceedings of the 2014 IEEE Symposium on Low-Power and High-Speed Chips, 2014

An impact of circuit scale on the performance of 3-D stacked arithmetic units.

[BibT_eX]

[DOI]

Hiroaki Kobayashi

Proceedings of the 2014 International 3D Systems Integration Conference, 2014

On-chip checkpointing with 3D-stacked memories.

[BibT_eX]

[DOI]

Proceedings of the 2014 International 3D Systems Integration Conference, 2014

2013

A Capacity-Aware Thread Scheduling Method Combined with Cache Partitioning to Reduce Inter-Thread Cache Conflicts.

[BibT_eX]

[DOI]

IEICE Trans. Inf. Syst., 2013

Design and evaluation of a media-oriented vector processor with a multi-banked cache memory.

[BibT_eX]

[DOI]

Proceedings of the 11th IEEE Symposium on Embedded Systems for Real-time Multimedia, 2013

A flexible insertion policy for dynamic cache resizing mechanisms.

[BibT_eX]

[DOI]

Proceedings of the 2013 IEEE Symposium on Low-Power and High-Speed Chips, 2013

Design of a 3-D stacked floating-point adder.

[BibT_eX]

[DOI]