Ryota Yasudo

According to our database, Ryota Yasudo authored at least 38 papers between 2014 and 2024.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of three.

2024

A low-latency memory-cube network with dual diagonal mesh topology and bypassed pipelines.

Masashi Oda, Kai Keida, Ryota Yasudo

Concurr. Comput. Pract. Exp., December, 2024

Power Optimized Design Framework for FPGA Clusters.

Kensuke Iizuka, Kohei Ito, Ryota Yasudo, Hideharu Amano

IPSJ Trans. Syst. LSI Des. Methodol., 2024

Solving the QAP by Two-Stage Graph Pointer Networks and Reinforcement Learning.

Satoko Iida, Ryota Yasudo

CoRR, 2024

2023

Designing low-diameter interconnection networks with multi-ported host-switch graphs.

Ryota Yasudo, Koji Nakano, Michihiro Koibuchi, Hiroki Matsutani, Hideharu Amano

Concurr. Comput. Pract. Exp., 2023

High-throughput FPGA implementation for quadratic unconstrained binary optimization.

Hiroshi Kagawa, Yasuaki Ito, Koji Nakano, Ryota Yasudo, Yuya Kawamata, Ryota Katsuki, Yusuke Tabata, Takashi Yazane, Kenichiro Hamano

Concurr. Comput. Pract. Exp., 2023

Simple iterative trial search for the maximum independent set problem optimized for the GPUs.

Tomohiro Imanaga, Koji Nakano, Ryota Yasudo, Yasuaki Ito, Yuya Kawamata, Ryota Katsuki, Yusuke Tabata, Takashi Yazane, Kenichiro Hamano

Concurr. Comput. Pract. Exp., 2023

Bandit-based Variable Fixing for Binary Optimization on GPU Parallel Computing.

Ryota Yasudo

Proceedings of the 31st Euromicro International Conference on Parallel, 2023

Amorphica: 4-Replica 512 Fully Connected Spin 336MHz Metamorphic Annealer with Programmable Optimization Strategy and Compressed-Spin-Transfer Multi-Chip Extension.

Kazushi Kawamura, Jaehoon Yu, Daiki Okonogi, Satoru Jimbo, Genta Inoue, Akira Hyodo, Ángel López García-Arias, Kota Ando, Bruno Hideki Fukushima-Kimura, Ryota Yasudo, Thiem Van Chu, Masato Motomura

Proceedings of the IEEE International Solid- State Circuits Conference, 2023

Performance Modeling and Scalability Analysis of Stream Computing in ESSPER FPGA Clusters.

Ryota Miyagi, Ryota Yasudo, Kentaro Sano, Hideki Takase

Proceedings of the International Conference on Field Programmable Technology, 2023

Dual Diagonal Mesh: An Optimal Memory Cube Network Under Geometric Constraints.

Masashi Oda, Kai Keida, Ryota Yasudo

Proceedings of the Eleventh International Symposium on Computing and Networking, CANDAR 2023, Matsue, Japan, November 28, 2023

2022

GPU-accelerated scalable solver with bit permutated cyclic-min algorithm for quadratic unconstrained binary optimization.

Ryota Yasudo, Koji Nakano, Yasuaki Ito, Ryota Katsuki, Yusuke Tabata, Takashi Yazane, Kenichiro Hamano

J. Parallel Distributed Comput., 2022

Graph-theoretic Formulation of QUBO for Scalable Local Search on GPUs.

Ryota Yasudo, Koji Nakano, Yasuaki Ito, Yuya Kawamata, Ryota Katsuki, Shiro Ozaki, Takashi Yazane, Kenichiro Hamano

Proceedings of the IEEE International Parallel and Distributed Processing Symposium, 2022

Elastic Sample Filter: An FPGA-based Accelerator for Bayesian Network Structure Learning.

Ryota Miyagi, Ryota Yasudo, Kentaro Sano, Hideki Takase

Proceedings of the International Conference on Field-Programmable Technology, 2022

Optimizing Application Mapping for Multi-FPGA Systems with Multi-ejection STDM Switches.

Kohei Ito, Ryota Yasudo, Hideharu Amano

Proceedings of the 32nd International Conference on Field-Programmable Logic and Applications, 2022

2021

Analytical Performance Estimation for Large-Scale Reconfigurable Dataflow Platforms.

Ryota Yasudo, José Gabriel de Figueiredo Coutinho, Ana Lucia Varbanescu, Wayne Luk, Hideharu Amano, Tobias Becker, Ce Guo

ACM Trans. Reconfigurable Technol. Syst., 2021

Efficient implementations of Bloom filter using block RAMs and DSP slices on the FPGA.

Takuma Wada, Naoki Matsumura, Ryota Yasudo, Koji Nakano, Yasuaki Ito

Concurr. Comput. Pract. Exp., 2021

Solving the sparse QUBO on multiple GPUs for Simulating a Quantum Annealer.

Tomohiro Imanaga, Koji Nakano, Ryota Yasudo, Yasuaki Ito, Yuya Kawamata, Ryota Katsuki, Shiro Ozaki, Takashi Yazane, Kenichiro Hamano

Proceedings of the Ninth International Symposium on Computing and Networking, 2021

2020

Traffic-Independent Multi-Path Routing for High-Throughput Data Center Networks.

Ryuta Kawano, Ryota Yasudo, Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano

IEICE Trans. Inf. Syst., 2020

A Generalized Theory Based on the Turn Model for Deadlock-Free Irregular Networks.

Ryuta Kawano, Ryota Yasudo, Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano

IEICE Trans. Inf. Syst., 2020

A Work-Time Optimal Parallel Exhaustive Search Algorithm for the QUBO and the Ising model, with GPU implementation.

Masaki Tao, Koji Nakano, Yasuaki Ito, Ryota Yasudo, Masaru Tatekawa, Ryota Katsuki, Takashi Yazane, Yoko Inaba

Proceedings of the 2020 IEEE International Parallel and Distributed Processing Symposium Workshops, 2020

Adaptive Bulk Search: Solving Quadratic Unconstrained Binary Optimization Problems on Multiple GPUs.

Ryota Yasudo, Koji Nakano, Yasuaki Ito, Masaru Tatekawa, Ryota Katsuki, Takashi Yazane, Yoko Inaba

Proceedings of the ICPP 2020: 49th International Conference on Parallel Processing, 2020

Fully-Pipelined Architecture for Simulated Annealing-based QUBO Solver on the FPGA.

Hiroshi Kagawa, Yasuaki Ito, Koji Nakano, Ryota Yasudo, Yuya Kawamata, Ryota Katsuki, Yusuke Tabata, Takashi Yazane, Kenichiro Hamano

Proceedings of the Eighth International Symposium on Computing and Networking, 2020

Efficient GPU Implementation for Solving the Maximum Independent Set Problem.

Tomohiro Imanaga, Koji Nakano, Masaki Tao, Ryota Yasudo, Yasuaki Ito, Yuya Kawamata, Ryota Katsuki, Yusuke Tabata, Takashi Yazane, Kenichiro Hamano

Proceedings of the Eighth International Symposium on Computing and Networking, 2020

Dual-Plane Isomorphic Hypercube Network.

Takeo Hosomi, Ryota Yasudo, Michihiro Koibuchi, Shinji Shimojo

Proceedings of the International Conference on High Performance Computing in Asia-Pacific Region, 2020

2019

Designing High-Performance Interconnection Networks with Host-Switch Graphs.

Ryota Yasudo, Michihiro Koibuchi, Koji Nakano, Hiroki Matsutani, Hideharu Amano

IEEE Trans. Parallel Distributed Syst., 2019

The Degree Diameter Problem for Host-Switch Graphs.

Ryota Yasudo, Koji Nakano

Proceedings of the Seventh International Symposium on Computing and Networking Workshops, 2019

Folded Bloom Filter for High Bandwidth Memory, with GPU Implementations.

Masatoshi Hayashikawa, Koji Nakano, Yasuaki Ito, Ryota Yasudo

Proceedings of the 2019 Seventh International Symposium on Computing and Networking, 2019

2018

k-Optimized Path Routing for High-Throughput Data Center Networks.

Ryuta Kawano, Ryota Yasudo, Hiroki Matsutani, Hideharu Amano

Proceedings of the Sixth International Symposium on Computing and Networking, 2018

Performance Estimation for Exascale Reconfigurable Dataflow Platforms.

Ryota Yasudo, José Gabriel F. Coutinho, Ana Lucia Varbanescu, Wayne Luk, Hideharu Amano, Tobias Becker

Proceedings of the International Conference on Field-Programmable Technology, 2018

Performance Prediction for Large-Scale Heterogeneous Platforms.

Ryota Yasudo, Ana Lucia Varbanescu, José Gabriel F. Coutinho, Wayne Luk, Hideharu Amano

Proceedings of the 26th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2018

2017

Scalable Networks-on-Chip with Elastic Links Demarcated by Decentralized Routers.

Ryota Yasudo, Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano, Tadao Nakamura

IEEE Trans. Computers, 2017

XYZ-Randomization using TSVs for Low-Latency Energy Efficient 3D-NoCs.

Hiroshi Nakahara, Ng. Anh Vu Doan, Ryota Yasudo, Hideharu Amano

Proceedings of the Eleventh IEEE/ACM International Symposium on Networks-on-Chip, 2017

3D Layout of Spidergon, Flattened Butterfly and Dragonfly on a Chip Stack with Inductive Coupling Through Chip Interface.

Hiroshi Nakahara, Ryota Yasudo, Hiroki Matsutani, Hideharu Amano, Michihiro Koibuchi

Proceedings of the 14th International Symposium on Pervasive Systems, 2017

Order/Radix Problem: Towards Low End-to-End Latency Interconnection Networks.

Ryota Yasudo, Michihiro Koibuchi, Koji Nakano, Hiroki Matsutani, Hideharu Amano

Proceedings of the 46th International Conference on Parallel Processing, 2017

HiRy: An Advanced Theory on Design of Deadlock-Free Adaptive Routing for Arbitrary Topologies.

Ryuta Kawano, Ryota Yasudo, Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano

Proceedings of the 23rd IEEE International Conference on Parallel and Distributed Systems, 2017

2015

On-Chip Decentralized Routers with Balanced Pipelines for Avoiding Interconnect Bottleneck.

Ryota Yasudo, Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano, Tadao Nakamura

Proceedings of the 9th International Symposium on Networks-on-Chip, 2015

2014

Design of a low power NoC router using Marching Memory Through type.

Ryota Yasudo, Takahiro Kagami, Hideharu Amano, Yasunobu Nakase, Masashi Watanabe, Tsukasa Oishi, Toru Shimizu, Tadao Nakamura

Proceedings of the Eighth IEEE/ACM International Symposium on Networks-on-Chip, 2014

A low power NoC router using the marching memory through type.

Ryota Yasudo, Takahiro Kagami, Hideharu Amano, Yasunobu Nakase, Masashi Watanabe, Tsukasa Oishi, Toru Shimizu, Tadao Nakamura

Proceedings of the 2014 IEEE Symposium on Low-Power and High-Speed Chips, 2014