Ryota Sekimoto
According to our database1,
Ryota Sekimoto
authored at least 10 papers
between 2010 and 2015.
Collaborative distances:
Collaborative distances:
Timeline
Legend:
Book In proceedings Article PhD thesis Dataset OtherLinks
On csauthors.net:
Bibliography
2015
An 8 bit 0.3-0.8 V 0.2-40 MS/s 2-bit/Step SAR ADC With Successively Activated Threshold Configuring Comparators in 40 nm CMOS.
IEEE Trans. Very Large Scale Integr. Syst., 2015
2014
An 8b extremely area efficient threshold configuring SAR ADC with source voltage shifting technique.
Proceedings of the 19th Asia and South Pacific Design Automation Conference, 2014
2013
A 0.5-V 5.2-fJ/Conversion-Step Full Asynchronous SAR ADC With Leakage Power Reduction Down to 650 pW by Boosted Self-Power Gating in 40-nm CMOS.
IEEE J. Solid State Circuits, 2013
A 4-10 bit, 0.4-1 V Power Supply, Power Scalable Asynchronous SAR-ADC in 40 nm-CMOS with Wide Supply Voltage Range SAR Controller.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2013
An Adaptive DAC Settling Waiting Time Optimized Ultra Low Voltage Asynchronous SAR ADC in 40 nm CMOS.
IEICE Trans. Electron., 2013
Proceedings of the 18th Asia and South Pacific Design Automation Conference, 2013
2012
A 0.5 V 1.1 MS/sec 6.3 fJ/Conversion-Step SAR-ADC With Tri-Level Comparator in 40 nm CMOS.
IEEE J. Solid State Circuits, 2012
An 8bit 0.35-0.8V 0.5-30MS/s 2bit/step SAR ADC with wide range threshold configuring comparator.
Proceedings of the 38th European Solid-State Circuit conference, 2012
2011
A 40nm 50S/s-8MS/s ultra low voltage SAR ADC with timing optimized asynchronous clock generator.
Proceedings of the 37th European Solid-State Circuits Conference, 2011
2010
A 0.5V 65nm-CMOS single phase clocked bootstrapped switch with rise time accelerator.
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2010