Ryosuke Noguchi

According to our database, Ryosuke Noguchi authored at least 6 papers between 2017 and 2019.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2019

Design of Crosstalk Noise Filter for Multi-Channel Transimpedance Amplifier.

Shinya Tanimura, Akira Tsuchiya, Ryosuke Noguchi, Toshiyuki Inoue, Keiji Kishine

Proceedings of the 32nd IEEE International System-on-Chip Conference, 2019

Suitable-Compensation Circuit Design for a PAM4 Transmitter in 180-nm CMOS.

Yudai Ichii, Ryosuke Noguchi, Toshiyuki Inoue, Akira Tsuchiya, Keiji Kishine

Proceedings of the 2019 International SoC Design Conference, 2019

2018

A 25-Gb/s 13 mW clock and data recovery using C²MOS D-flip-flop in 65-nm CMOS.

Ryosuke Noguchi, Kosuke Furuichi, Hiromu Uemura, Toshiyuki Inoue, Akira Tsuchiya, Keiji Kishine, Hiroaki Katsurai, Shinsuke Nakano, Hideyuki Nosaka

Proceedings of the 2018 International Symposium on VLSI Design, 2018

Low-Power and High-Linearity Inductorless Low-Noise Amplifiers with Active-Shunt-Feedback in 65-nm CMOS Technology.

Toshiyuki Inoue, Ryosuke Noguchi, Akira Tsuchiya, Keiji Kishine, Hidetoshi Onodera

Proceedings of the IEEE 61st International Midwest Symposium on Circuits and Systems, 2018

A 25-Gb/s Low-Power Clock and Data Recovery with an Active-Stabilizing CML-CMOS Conversion.

Ryosuke Noguchi, Atsuto Imajo, Toshiyuki Inoue, Akira Tsuchiya, Keiji Kishine

Proceedings of the 25th IEEE International Conference on Electronics, Circuits and Systems, 2018

2017

25-Gb/s clock and data recovery IC using latch-load combined with CML buffer circuit for delay generation with 65-nm CMOS.

Tomonori Tanaka, Kosuke Furuichi, Hiromu Uemura, Ryosuke Noguchi, Natsuyuki Koda, Koki Arauchi, Daichi Omoto, Hiromi Inaba, Keiji Kishine, Shinsuke Nakano, Masafumi Nogawa, Hideyuki Nosaka

Proceedings of the IEEE International Symposium on Circuits and Systems, 2017