Ryohei Kobayashi

Orcid: 0000-0003-2175-9828

Affiliations:
  • Institute of Science Tokyo, Tokyo, Japan


According to our database1, Ryohei Kobayashi authored at least 41 papers between 2012 and 2024.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Bibliography

2024
Improving Performance on Replica-Exchange Molecular Dynamics Simulations by Optimizing GPU Core Utilization.
Proceedings of the 53rd International Conference on Parallel Processing, 2024

Using Intel oneAPI for Multi-hybrid Acceleration Programming with GPU and FPGA Coupling.
Proceedings of the International Conference on High Performance Computing in Asia-Pacific Region Workshops, 2024

CHARM-SYCL & IRIS: A Tool Chain for Performance Portability on Extremely Heterogeneous Systems.
Proceedings of the 20th IEEE International Conference on e-Science, 2024

Using SYCLomatic to Migrate CUDA Code to oneAPI Adapting NVIDIA GPU.
Proceedings of the IEEE International Conference on Cluster Computing, 2024

Preliminary Evaluation of Kyokko for Inter-FPGA Communication Framework CIRCUS.
Proceedings of the IEEE International Conference on Cluster Computing, 2024

Preliminary Performance Evaluation of Grace-Hopper GH200.
Proceedings of the IEEE International Conference on Cluster Computing, 2024

2023
Data Transfer API and its Performance Model for Rank-Level Approximate Computing on HPC Systems.
Int. J. Netw. Comput., 2023

OpenACC Unified Programming Environment for Multi-hybrid Acceleration with GPU and FPGA.
Proceedings of the High Performance Computing, 2023

CHARM-SYCL: New Unified Programming Environment for Multiple Accelerator Types.
Proceedings of the SC '23 Workshops of The International Conference on High Performance Computing, 2023

GPU-FPGA-accelerated Radiative Transfer Simulation with Inter-FPGA Communication.
Proceedings of the International Conference on High Performance Computing in Asia-Pacific Region, 2023

Implementation and Performance Evaluation of Collective Communications Using CIRCUS on Multiple FPGAs.
Proceedings of the HPC Asia 2023 Workshops, 2023

Performance improvement by enhancing spatial parallelism on FPGA for HPC applications.
Proceedings of the IEEE International Conference on Cluster Computing, 2023

2022
An Open-source FPGA Library for Data Sorting.
J. Inf. Process., 2022

Accelerating Radiative Transfer Simulation on NVIDIA GPUs with OpenACC.
Proceedings of the Parallel and Distributed Computing, Applications and Technologies, 2022

Performance Evaluation of Data Transfer API for Rank Level Approximate Computing on HPC Systems.
Proceedings of the IEEE International Parallel and Distributed Processing Symposium, 2022

Cygnus - World First Multihybrid Accelerated Cluster with GPU and FPGA Coupling.
Proceedings of the Workshop Proceedings of the 51st International Conference on Parallel Processing, 2022

Multi-hetero Acceleration by GPU and FPGA for Astrophysics Simulation on oneAPI Environment.
Proceedings of the HPC Asia 2022: International Conference on High Performance Computing in Asia-Pacific Region, Virtual Event, Japan, January 12, 2022

Performance Evaluation on GPU-FPGA Accelerated Computing Considering Interconnections between Accelerators.
Proceedings of the HEART 2022: International Symposium on Highly-Efficient Accelerators and Reconfigurable Technologies, Tsukuba, Japan, June 9, 2022

Implementation and Performance Evaluation of Memory System Using Addressable Cache for HPC Applications on HBM2 Equipped FPGAs.
Proceedings of the Euro-Par 2022: Parallel Processing Workshops, 2022

An FPGA-based Accelerator for Regular Path Queries over Edge-labeled Graphs.
Proceedings of the IEEE International Conference on Big Data, 2022

2021
Performance Evaluation of OpenCL-Enabled Inter-FPGA Optical Link Communication Framework CIRCUS and SMI.
Proceedings of the HPC Asia 2021: The International Conference on High Performance Computing in Asia-Pacific Region, 2021

A Sorting Library for FPGA Implementation in OpenCL Programming.
Proceedings of the HEART '21: 11th International Symposium on Highly Efficient Accelerators and Reconfigurable Technologies, 2021

An efficient RTL buffering scheme for an FPGA-accelerated simulation of diffuse radiative transfer.
Proceedings of the International Conference on Field-Programmable Technology, 2021

HBM2 Memory System for HPC Applications on an FPGA.
Proceedings of the IEEE International Conference on Cluster Computing, 2021

2020
Multi-Hybrid Accelerated Simulation by GPU and FPGA on Radiative Transfer Simulation in Astrophysics.
J. Inf. Process., 2020

OpenCL-enabled Parallel Raytracing for Astrophysical Application on Multiple FPGAs with Optical Links.
Proceedings of the 2020 IEEE/ACM International Workshop on Heterogeneous High-performance Reconfigurable Computing, 2020

Performance Evaluation of Pipelined Communication Combined with Computation in OpenCL Programming on FPGA.
Proceedings of the 2020 IEEE International Parallel and Distributed Processing Symposium Workshops, 2020

Toward OpenACC-enabled GPU-FPGA Accelerated Computing.
Proceedings of the IEEE International Conference on Cluster Computing, 2020

Accelerating Radiative Transfer Simulation with GPU-FPGA Cooperative Computation.
Proceedings of the 31st IEEE International Conference on Application-specific Systems, 2020

2019
GPU-FPGA Heterogeneous Computing with OpenCL-Enabled Direct Memory Access.
Proceedings of the IEEE International Parallel and Distributed Processing Symposium Workshops, 2019

Parallel Processing on FPGA Combining Computation and Communication in OpenCL Programming.
Proceedings of the IEEE International Parallel and Distributed Processing Symposium Workshops, 2019

2018
ArchHDL: A Novel Hardware RTL Modeling and High-Speed Simulation Environment.
IEICE Trans. Inf. Syst., 2018

OpenCL-ready High Speed FPGA Network for Reconfigurable High Performance Computing.
Proceedings of the International Conference on High Performance Computing in Asia-Pacific Region, 2018

Accelerating Space Radiative Transfer on FPGA using OpenCL.
Proceedings of the 9th International Symposium on Highly-Efficient Accelerators and Reconfigurable Technologies, 2018

2017
A High Performance FPGA-Based Sorting Accelerator with a Data Compression Mechanism.
IEICE Trans. Inf. Syst., 2017

2016
A High-speed Verilog HDL Simulation Method using a Lightweight Translator.
SIGARCH Comput. Archit. News, 2016

2015
Reconfigurable IBM PC Compatible SoC for Computer Architecture Education and Research.
Proceedings of the IEEE 9th International Symposium on Embedded Multicore/Many-core Systems-on-Chip, 2015

FACE: Fast and Customizable Sorting Accelerator for Heterogeneous Many-core Systems.
Proceedings of the IEEE 9th International Symposium on Embedded Multicore/Many-core Systems-on-Chip, 2015

Effective Parallel Simulation of ArchHDL under Manycore Environment.
Proceedings of the Third International Symposium on Computing and Networking, 2015

A Challenge of Portable and High-Speed FPGA Accelerator.
Proceedings of the Applied Reconfigurable Computing - 11th International Symposium, 2015

2012
Towards a Low-Power Accelerator of Many FPGAs for Stencil Computations.
Proceedings of the Third International Conference on Networking and Computing, 2012


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