Ryo Haga

According to our database, Ryo Haga authored at least 4 papers between 1995 and 2001.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of five.

2001

Interface socket design methodology to generate embedded DRAM macros.

Ryo Haga, Tetsuya Kaneko, Atsushi Nakayama, Shinji Miyano, Hiroyuki Takenaka, Kenji Numata, Hiroyuki Koinuma, Takehiko Hojo, Akikuni Sato, Toshiyuki Kouchi, Kenichiro Mimoto, Masaaki Tazawa, Tsutomu Ohkubo, Takanori Andou, Tetsuya Amano

Proceedings of the IEEE 2001 Custom Integrated Circuits Conference, 2001

2000

Dynamically shift-switched dataline redundancy suitable for DRAM macro with wide data bus.

Toshimasa Namekawa, Shinji Miyano, Ryo Fukuda, Ryo Haga, Osamu Wada, Hironori Banba, Satoru Takeda, Kazuhiro Suda, Kenichiro Mimoto, Satoshi Yamaguchi, Tsutomu Ohkubo, Hiroshi Takato, Kenji Numata

IEEE J. Solid State Circuits, 2000

1998

A configurable DRAM macro design for 2112 derivative organizations to be synthesized using a memory generator.

Tomoaki Yabe, Shinji Miyano, Katsuhiko Sato, Masaharu Wada, Ryo Haga, Osamu Wada, Motohiro Enkaku, Takehiko Hojyo, Kenichiro Mimoto, Masaaki Tazawa, Tsutomu Ohkubo, Kenji Numata

IEEE J. Solid State Circuits, 1998

1995

A 1.6 Gbyte/s data transfer rate 8 Mb embedded DRAM.

Shinji Miyano, Kenji Numata, Katsuhiko Sato, Tomoaki Yabe, Masaharu Wada, Ryo Haga, Motohiro Enkaku, Masazumi Shiochi, Yutaka Kawashima, Masayuki Iwase, Masahisa Ohgata, Junpei Kumagai, Takeshi Yoshida, Masaomi Sakurai, Seiji Kaki, Narutoshi Yanagiya, Hiroshi Shinya, Tohm Fumyama, Paul Hansen, Marc Hannah, Michael Nagy, Anan Nagarajan, Mana Rungsea

IEEE J. Solid State Circuits, November, 1995