Ryan Kastner

Orcid: 0000-0001-9062-5570

Affiliations:
  • University of California, San Diego, USA


According to our database1, Ryan Kastner authored at least 225 papers between 2000 and 2024.

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Bibliography

2024
Turn on, Tune in, and Listen up: Maximizing Side-Channel Recovery in Cross-Platform Time-to-Digital Converters.
ACM Trans. Reconfigurable Technol. Syst., September, 2024

Tailor: Altering Skip Connections for Resource-Efficient Inference.
ACM Trans. Reconfigurable Technol. Syst., March, 2024

CGRA4ML: A Framework to Implement Modern Neural Networks for Scientific Edge Computing.
CoRR, 2024

Architectural Implications of Neural Network Inference for High Data-Rate, Low-Latency Scientific Applications.
CoRR, 2024

TOP: Towards Open & Predictable Heterogeneous SoCs.
CoRR, 2024


Pentimento: Data Remanence in Cloud FPGAs.
Proceedings of the 29th ACM International Conference on Architectural Support for Programming Languages and Operating Systems, 2024

2023
Isadora: automated information-flow property generation for hardware security verification.
J. Cryptogr. Eng., November, 2023

A Framework for Design, Verification, and Management of SoC Access Control Systems.
IEEE Trans. Computers, February, 2023

Security Verification of the OpenTitan Hardware Root of Trust.
IEEE Secur. Priv., 2023

Information Flow Coverage Metrics for Hardware Security Verification.
CoRR, 2023

Tailor: Altering Skip Connections for Resource-Efficient Inference.
CoRR, 2023

Special Session: CAD for Hardware Security - Promising Directions for Automation of Security Assurance.
Proceedings of the 41st IEEE VLSI Test Symposium, 2023

Adapting Skip Connections for Resource-Efficient FPGA Inference.
Proceedings of the 2023 ACM/SIGDA International Symposium on Field Programmable Gate Arrays, 2023

Turn on, Tune in, Listen up: Maximizing Side-Channel Recovery in Time-to-Digital Converters.
Proceedings of the 2023 ACM/SIGDA International Symposium on Field Programmable Gate Arrays, 2023

Within-Camera Multilayer Perceptron DVS Denoising.
Proceedings of the IEEE/CVF Conference on Computer Vision and Pattern Recognition, 2023

Automated Generation, Verification, and Ranking of Secure SoC Access Control Policies.
Proceedings of Cyber-Physical Systems and Internet of Things Week 2023, 2023

Junkyard Computing: Repurposing Discarded Smartphones to Minimize Carbon.
Proceedings of the 28th ACM International Conference on Architectural Support for Programming Languages and Operating Systems, 2023

2022
Sherlock: A Multi-Objective Design Space Exploration Framework.
ACM Trans. Design Autom. Electr. Syst., 2022

Cut and Forward: Safe and Secure Communication for FPGA System on Chips.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022

ARTe: Providing real-time multitasking to Arduino.
J. Syst. Softw., 2022

Toward Hardware Security Property Generation at Scale.
IEEE Secur. Priv., 2022

Renée: New Life for Old Phones.
IEEE Embed. Syst. Lett., 2022

A Remote Control System for Emergency Ventilators During SARS-CoV-2.
IEEE Embed. Syst. Lett., 2022

Hardware Information Flow Tracking.
ACM Comput. Surv., 2022

Open-source FPGA-ML codesign for the MLPerf Tiny Benchmark.
CoRR, 2022

Underwater Depth Calibration Using a Commercial Depth Camera.
Proceedings of the WUWNet 2022: The 16th International Conference on Underwater Networks & Systems, 2022

Automating hardware security property generation: invited.
Proceedings of the DAC '22: 59th ACM/IEEE Design Automation Conference, San Francisco, California, USA, July 10, 2022

Integrating Information Flow Tracking into High-Level Synthesis Design Flow.
Behavioral Synthesis for Hardware Security, 2022

2021
$O(N)$O(N)-Space Spatiotemporal Filter for Reducing Noise in Neuromorphic Vision Sensors.
IEEE Trans. Emerg. Top. Comput., 2021

An Overview of Hardware Security and Trust: Threats, Countermeasures, and Design Tools.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2021

A more precise way to localize animals using drones.
J. Field Robotics, 2021

Applications and Techniques for Fast Machine Learning in Science.
CoRR, 2021

Architecture of a Junkyard Datacenter.
CoRR, 2021

AKER: A Design and Verification Framework for Safe andSecure SoC Access Control.
CoRR, 2021

A Methodology For Creating Information Flow Specifications of Hardware Designs.
CoRR, 2021

Hardware-efficient Residual Networks for FPGAs.
CoRR, 2021

Special Session: CAD for Hardware Security - Automation is Key to Adoption of Solutions.
Proceedings of the 39th IEEE VLSI Test Symposium, 2021

Pyrenote: a Web-based, Manual Annotation Tool for Passive Acoustic Monitoring.
Proceedings of the IEEE 18th International Conference on Mobile Ad Hoc and Smart Systems, 2021

ASLR: An Adaptive Scheduler for Learning Rate.
Proceedings of the International Joint Conference on Neural Networks, 2021

Aker: A Design and Verification Framework for Safe and Secure SoC Access Control.
Proceedings of the IEEE/ACM International Conference On Computer Aided Design, 2021

iSTELLAR: intermittent Signature aTtenuation Embedded CRYPTO with Low-Level metAl Routing.
Proceedings of the IEEE/ACM International Conference On Computer Aided Design, 2021

S2N2: A FPGA Accelerator for Streaming Spiking Neural Networks.
Proceedings of the FPGA '21: The 2021 ACM/SIGDA International Symposium on Field Programmable Gate Arrays, Virtual Event, USA, February 28, 2021

Classifying Computations on Multi-Tenant FPGAs.
Proceedings of the FPGA '21: The 2021 ACM/SIGDA International Symposium on Field Programmable Gate Arrays, Virtual Event, USA, February 28, 2021

A Tunable Dual-Edge Time-to-Digital Converter.
Proceedings of the 29th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2021

Classifying Computations on Multi-Tenant FPGAs.
Proceedings of the 58th ACM/IEEE Design Automation Conference, 2021

Isadora: Automated Information Flow Property Generation for Hardware Designs.
Proceedings of the ASHES@CCS 2021: Proceedings of the 5th Workshop on Attacks and Solutions in Hardware Security, 2021

2020
Memory-Based High-Level Synthesis Optimizations Security Exploration on the Power Side-Channel.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020

A Unified Model for Gate Level Propagation Analysis.
CoRR, 2020

Patient Specific Biomechanics Are Clinically Significant In Accurate Computer Aided Surgical Image Guidance.
CoRR, 2020

Real-time Automatic Modulation Classification using RFSoC.
Proceedings of the 2020 IEEE International Parallel and Distributed Processing Symposium Workshops, 2020

2019
Introduction to the Special Section on Security in FPGA-accelerated Cloud and Datacenters.
ACM Trans. Reconfigurable Technol. Syst., 2019

D-SEA: The Underwater Depth Sensing Device for Standalone Time-Averaged Measurements.
Proceedings of the 16th IEEE International Conference on Mobile Ad Hoc and Sensor Systems Workshops, 2019

Benchmarking Video with the Surgical Image Registration Generator (SIRGn) Baseline.
Proceedings of the Advances in Visual Computing, 2019

FastWave: Accelerating Autoregressive Convolutional Neural Networks on FPGA.
Proceedings of the International Conference on Computer-Aided Design, 2019

Holistic Power Side-Channel Leakage Assessment: Towards a Robust Multidimensional Metric.
Proceedings of the International Conference on Computer-Aided Design, 2019

VeriSketch: Synthesizing Secure Hardware Designs with Timing-Sensitive Information Flow Properties.
Proceedings of the 2019 ACM SIGSAC Conference on Computer and Communications Security, 2019

FPGA Architectures for Real-time Dense SLAM.
Proceedings of the 30th IEEE International Conference on Application-specific Systems, 2019

2018
Synthesizable Higher-Order Functions for C++.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018

Quantitative Analysis of Timing Channel Security in Cryptographic Hardware Design.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018

A hardware accelerated system for high throughput cellular image analysis.
J. Parallel Distributed Comput., 2018

Parallel Programming for FPGAs.
CoRR, 2018

Symbolic execution based test-patterns generation algorithm for hardware Trojan detection.
Comput. Secur., 2018

Self-Localization of a Deforming Swarm of Underwater Vehicles Using Impulsive Sound Sources of Opportunity.
IEEE Access, 2018

Hiding Intermittent Information Leakage with Architectural Support for Blinking.
Proceedings of the 45th ACM/IEEE Annual International Symposium on Computer Architecture, 2018

Property specific information flow analysis for hardware security verification.
Proceedings of the International Conference on Computer-Aided Design, 2018

Everyone's a Critic: A Tool for Exploring RISC-V Projects.
Proceedings of the 28th International Conference on Field Programmable Logic and Applications, 2018

A FPGA Accelerator for Real-Time 3D Non-rigid Registration Using Tree Reweighted Message Passing and Dynamic Markov Random Field Generation.
Proceedings of the 28th International Conference on Field Programmable Logic and Applications, 2018

Examining the consequences of high-level synthesis optimizations on power side-channel.
Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018

PynqCopter - An Open-source FPGA Overlay for UAVs.
Proceedings of the IEEE International Conference on Big Data (IEEE BigData 2018), 2018

2017
Identifying and Measuring Security Critical Path for Uncovering Circuit Vulnerabilities.
Proceedings of the 18th International Workshop on Microprocessor and SOC Test and Verification, 2017

Radio receiver design for Unmanned Aerial wildlife tracking.
Proceedings of the 2017 International Conference on Computing, 2017

A streaming clustering approach using a heterogeneous system for big data analysis.
Proceedings of the 2017 IEEE/ACM International Conference on Computer-Aided Design, 2017

Why you should care about don't cares: Exploiting internal don't care conditions for hardware Trojans.
Proceedings of the 2017 IEEE/ACM International Conference on Computer-Aided Design, 2017

Clepsydra: Modeling timing flows in hardware designs.
Proceedings of the 2017 IEEE/ACM International Conference on Computer-Aided Design, 2017

Register transfer level information flow tracking for provably secure hardware design.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017

Arbitrary Precision and Complexity Tradeoffs for Gate-Level Information Flow Tracking.
Proceedings of the 54th Annual Design Automation Conference, 2017

An Architecture for Learning Stream Distributions with Application to RNG Testing.
Proceedings of the 54th Annual Design Automation Conference, 2017

A message from the general chair and program chair.
Proceedings of the 28th IEEE International Conference on Application-specific Systems, 2017

2016
Detecting Hardware Trojans with Gate-Level Information-Flow Tracking.
Computer, 2016

Autonomous acoustic trigger for distributed underwater visual monitoring systems.
Proceedings of the 11th ACM International Conference on Underwater Networks & Systems, 2016

Detection and time-of-arrival estimation of underwater acoustic signals.
Proceedings of the 17th IEEE International Workshop on Signal Processing Advances in Wireless Communications, 2016

Towards Property Driven Hardware Security.
Proceedings of the 17th International Workshop on Microprocessor and SOC Test and Verification, 2016

Imprecise security: quality and complexity tradeoffs for hardware information flow tracking.
Proceedings of the 35th International Conference on Computer-Aided Design, 2016

Spector: An OpenCL FPGA benchmark suite.
Proceedings of the 2016 International Conference on Field-Programmable Technology, 2016

Resolve: Generation of High-Performance Sorting Architectures from High-Level Synthesis.
Proceedings of the 2016 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2016

Tinker: Generating Custom Memory Architectures for Altera's OpenCL Compiler.
Proceedings of the 24th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2016

Adaptive Threshold Non-Pareto Elimination: Re-thinking machine learning for system level design space exploration on FPGAs.
Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition, 2016

Composable, parameterizable templates for high-level synthesis.
Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition, 2016

Quantifying hardware security using joint information flow analysis.
Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition, 2016

2015
RIFFA 2.1: A Reusable Integration Framework for FPGA Accelerators.
ACM Trans. Reconfigurable Technol. Syst., 2015

ToA-TS: Time of arrival based joint time synchronization and tracking for mobile underwater systems.
Ad Hoc Networks, 2015

Real-time collaborative tracking for underwater networked systems.
Ad Hoc Networks, 2015

Scaling the Annotation of Subtidal Marine Habitats.
Proceedings of the 10th International Conference on Underwater Networks & Systems, 2015

Quantifying Timing-Based Information Flow in Cryptographic Hardware.
Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2015

A scalable FPGA architecture for nonnegative least squares problems.
Proceedings of the 25th International Conference on Field Programmable Logic and Applications, 2015

2014
Gate-Level Information Flow Tracking for Security Lattices.
ACM Trans. Design Autom. Electr. Syst., 2014

Leveraging Gate-Level Properties to Identify Hardware Timing Channels.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2014

Networks on Chip with Provable Security Properties.
IEEE Micro, 2014

Enabling FPGAs for the Masses.
CoRR, 2014

Small Unmanned Aerial Vehicle System for Wildlife Radio Collar Tracking.
Proceedings of the 11th IEEE International Conference on Mobile Ad Hoc and Sensor Systems, 2014

Real-time 3D reconstruction for FPGAs: A case study for evaluating the performance, area, and programmability trade-offs of the Altera OpenCL SDK.
Proceedings of the 2014 International Conference on Field-Programmable Technology, 2014

Hardware accelerated novel optical de novo assembly for large-scale genomes.
Proceedings of the 24th International Conference on Field Programmable Logic and Applications, 2014

High throughput channel tracking for JTRS wireless channel emulation.
Proceedings of the 24th International Conference on Field Programmable Logic and Applications, 2014

Improving FPGA accelerated tracking with multiple online trained classifiers.
Proceedings of the 24th International Conference on Field Programmable Logic and Applications, 2014

FPGA Accelerated Online Boosting for Multi-target Tracking.
Proceedings of the 22nd IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2014

Sapper: a language for hardware-level security policy enforcement.
Proceedings of the Architectural Support for Programming Languages and Operating Systems, 2014

Energy efficient canonical huffman encoding.
Proceedings of the IEEE 25th International Conference on Application-Specific Systems, 2014

2013
A 3-D Split Manufacturing Approach to Trustworthy System Development.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2013

A software-based dynamic-warp scheduling approach for load-balancing the Viola-Jones face detection algorithm on GPUs.
J. Parallel Distributed Comput., 2013

Design of a Reconfigurable Acoustic Modem for Underwater Sensor Networks.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2013

Expanding Gate Level Information Flow Tracking for Multilevel Security.
IEEE Embed. Syst. Lett., 2013

Eliminating Timing Information Flows in a Mix-Trusted System-on-Chip.
IEEE Des. Test, 2013

Joint time synchronization and tracking for mobile underwater systems.
Proceedings of the Conference on Underwater Networks and Systems, 2013

Position paper: Sapper - a language for provable hardware policy enforcement.
Proceedings of the 2013 ACM SIGPLAN Workshop on Programming Languages and Analysis for Security, 2013

SurfNoC: a low latency and provably non-interfering approach to secure networks-on-chip.
Proceedings of the 40th Annual International Symposium on Computer Architecture, 2013

A low-power Adaboost-based object detection processor using Haar-like features.
Proceedings of the IEEE Third International Conference on Consumer Electronics, 2013

A FPGA design for high speed feature extraction from a compressed measurement stream.
Proceedings of the 23rd International Conference on Field programmable Logic and Applications, 2013

A hardware accelerated approach for imaging flow cytometry.
Proceedings of the 23rd International Conference on Field programmable Logic and Applications, 2013

RIFFA 2.0: A reusable integration framework for FPGA accelerators.
Proceedings of the 23rd International Conference on Field programmable Logic and Applications, 2013

A practical testing framework for isolating hardware timing channels.
Proceedings of the Design, Automation and Test in Europe, 2013

2012
On the Complexity of Generating Gate Level Information Flow Tracking Logic.
IEEE Trans. Inf. Forensics Secur., 2012

Designing an Adaptive Acoustic Modem for Underwater Sensor Networks.
IEEE Embed. Syst. Lett., 2012

Real-time collaborative tracking for underwater networked systems.
Proceedings of the Conference on Under Water Networks, 2012

Simultaneous information flow security and circuit redundancy in Boolean gates.
Proceedings of the 2012 IEEE/ACM International Conference on Computer-Aided Design, 2012

Circuit Primitives for Monitoring Information Flow and Enabling Redundancy.
Proceedings of the Hardware and Software: Verification and Testing, 2012

Sensor platforms for multimodal underwater monitoring.
Proceedings of the 2012 International Green Computing Conference, 2012

FPGA-GPU-CPU heterogenous architecture for real-time cardiac physiological optical mapping.
Proceedings of the 2012 International Conference on Field-Programmable Technology, 2012

Designing a hardware in the loop wireless digital channel emulator for software defined radio.
Proceedings of the 2012 International Conference on Field-Programmable Technology, 2012

RIFFA: A Reusable Integration Framework for FPGA Accelerators.
Proceedings of the 2012 IEEE 20th Annual International Symposium on Field-Programmable Custom Computing Machines, 2012

GPU acceleration of optical mapping algorithm for cardiac electrophysiology.
Proceedings of the Annual International Conference of the IEEE Engineering in Medicine and Biology Society, 2012

A Qualitative Security Analysis of a New Class of 3-D Integrated Crypto Co-processors.
Proceedings of the Cryptography and Security: From Theory to Applications, 2012

2011
Integrating Embedded Computing Systems Into High School and Early Undergraduate Education.
IEEE Trans. Educ., 2011

Simulate and Eliminate: A Top-to-Bottom Design Methodology for Automatic Generation of Application Specific Architectures.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2011

Theoretical Fundamentals of Gate Level Information Flow Tracking.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2011

Crafting a usable microkernel, processor, and I/O system with strict and provable information flow security.
Proceedings of the 38th International Symposium on Computer Architecture (ISCA 2011), 2011

Design and Implementation of an FPGA-Based Real-Time Face Recognition System.
Proceedings of the IEEE 19th Annual International Symposium on Field-Programmable Custom Computing Machines, 2011

Information flow isolation in I2C and USB.
Proceedings of the 48th Design Automation Conference, 2011

JBoost Optimization of Color Detectors for Autonomous Underwater Vehicle Navigation.
Proceedings of the Computer Analysis of Images and Patterns, 2011

2010
Security Primitives for Reconfigurable Hardware-Based Systems.
ACM Trans. Reconfigurable Technol. Syst., 2010

GUSTO: An automatic generation and optimization tool for matrix inversion architectures.
ACM Trans. Embed. Comput. Syst., 2010

Layout Aware Optimization of High Speed Fixed Coefficient FIR Filters for FPGAs.
Int. J. Reconfigurable Comput., 2010

Design of a Low-Cost Underwater Acoustic Modem.
IEEE Embed. Syst. Lett., 2010

R&D of a dual mode acoustic modem testbed for shallow water channels.
Proceedings of the Workshop on Underwater Networks, 2010

Channel Equalization Based on Data Reuse LMS Algorithm for Shallow Water Acoustic Communication.
Proceedings of the IEEE International Conference on Sensor Networks, 2010

Hardware Implementation of Symbol Synchronization for Underwater FSK.
Proceedings of the IEEE International Conference on Sensor Networks, 2010

Field Programmable Gate Array Implementation of Parts-Based Object Detection for Real Time Video Applications.
Proceedings of the International Conference on Field Programmable Logic and Applications, 2010

Accelerating Viola-Jones Face Detection to FPGA-Level Using GPUs.
Proceedings of the 18th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2010

Increased Performace of FPGA-Based Color Classification System.
Proceedings of the 18th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2010

Theoretical analysis of gate level information flow tracking.
Proceedings of the 47th Design Automation Conference, 2010

Hardware trust implications of 3-D integration.
Proceedings of the 5th Workshop on Embedded Systems Security, 2010

Hardware assistance for trustworthy systems through 3-D integration.
Proceedings of the Twenty-Sixth Annual Computer Security Applications Conference, 2010

2009
Architectural optimization of decomposition algorithms for wireless communication systems.
Proceedings of the 2009 IEEE Wireless Communications and Networking Conference, 2009

Hardware acceleration of multi-view face detection.
Proceedings of the IEEE 7th Symposium on Application Specific Processors, 2009

Energy benefits of reconfigurable hardware for use in underwater sensor nets.
Proceedings of the 23rd IEEE International Symposium on Parallel and Distributed Processing, 2009

Fpga-based face detection system using Haar classifiers.
Proceedings of the ACM/SIGDA 17th International Symposium on Field Programmable Gate Arrays, 2009

Bit Error Rate, Power and Area Analysis of Multiple FPGA Implementations of Underwater FSK.
Proceedings of the 2009 International Conference on Engineering of Reconfigurable Systems & Algorithms, 2009

Xquasher: a tool for efficient computation of multiple linear expressions.
Proceedings of the 46th Design Automation Conference, 2009

Parallelized Architecture of Multiple Classifiers for Face Detection.
Proceedings of the 20th IEEE International Conference on Application-Specific Systems, 2009

2008
Designing secure systems on reconfigurable hardware.
ACM Trans. Design Autom. Electr. Syst., 2008

Managing Security in FPGA-Based Embedded Systems.
IEEE Des. Test Comput., 2008

Enforcing memory policy specifications in reconfigurable hardware.
Comput. Secur., 2008

An FPGA Design Space Exploration Tool for Matrix Inversion Architectures.
Proceedings of the IEEE Symposium on Application Specific Processors, 2008

Survey of hardware platforms for an energy efficient implementation of matching pursuits algorithm for shallow water networks.
Proceedings of the Third Workshop on Underwater Networks, 2008

Trustworthy System Security through 3-D Integrated Hardware.
Proceedings of the IEEE International Workshop on Hardware-Oriented Security and Trust, 2008

Automatic generation of decomposition based matrix inversion architectures.
Proceedings of the 2008 International Conference on Field-Programmable Technology, 2008

Threats and Challenges in Reconfigurable Hardware Security.
Proceedings of the 2008 International Conference on Engineering of Reconfigurable Systems & Algorithms, 2008

Design space exploration of a cooperative MIMO receiver for reconfigurable architectures.
Proceedings of the 19th IEEE International Conference on Application-Specific Systems, 2008

2007
Algebraic Methods for Optimizing Constant Multiplications in Linear Systems.
J. VLSI Signal Process., 2007

Exploring time/resource trade-offs by solving dual scheduling problems with the ant colony optimization.
ACM Trans. Design Autom. Electr. Syst., 2007

Ant Colony Optimizations for Resource- and Timing-Constrained Operation Scheduling.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2007

Implementation of the Alamouti OSTBC to a Distributed Set of Single-Antenna Wireless Nodes.
Proceedings of the IEEE Wireless Communications and Networking Conference, 2007

Moats and Drawbridges: An Isolation Primitive for Reconfigurable Hardware Based Systems.
Proceedings of the 2007 IEEE Symposium on Security and Privacy (S&P 2007), 2007

A pageable, defect-tolerant nanoscale memory system.
Proceedings of the 2007 IEEE International Symposium on Nanoscale Architectures, 2007

Combining static and dynamic defect-tolerance techniques for nanoscale memory systems.
Proceedings of the 2007 International Conference on Computer-Aided Design, 2007

2006
Statistical Analysis and Design of HARP FPGAs.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2006

Optimizing Polynomial Expressions by Algebraic Factorization and Common Subexpression Elimination.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2006

Application partitioning on programmable platforms using the ant colony optimization.
J. Embed. Comput., 2006

Design of a low-cost acoustic modem for moored oceanographic applications.
Proceedings of the First Workshop on Underwater Networks, WUWNET 2006, Los Angeles, CA, 2006

FPGA Implementation of High Speed FIR Filters Using Add and Shift Method.
Proceedings of the 24th International Conference on Computer Design (ICCD 2006), 2006

On the use of Bloom filters for defect maps in nanocomputing.
Proceedings of the 2006 International Conference on Computer-Aided Design, 2006

Carrier Offset and Channel Estimation for Cooperative MIMO Sensor Networks.
Proceedings of the Global Telecommunications Conference, 2006. GLOBECOM '06, San Francisco, CA, USA, 27 November, 2006

High speed FIR filter implementation using add and shift method.
Proceedings of the ACM/SIGDA 14th International Symposium on Field Programmable Gate Arrays, 2006

Defect-Tolerant Nanocomputing Using Bloom Filters.
Proceedings of the 14th IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM 2006), 2006

Policy-Driven Memory Protection for Reconfigurable Hardware.
Proceedings of the Computer Security, 2006

Layout driven data communication optimization for high level synthesis.
Proceedings of the Conference on Design, Automation and Test in Europe, 2006

Optimizing high speed arithmetic circuits using three-term extraction.
Proceedings of the Conference on Design, Automation and Test in Europe, 2006

Design space exploration using time and resource duality with the ant colony optimization.
Proceedings of the 43rd Design Automation Conference, 2006

Leakage power reduction of embedded memories on FPGAs through location assignment.
Proceedings of the 43rd Design Automation Conference, 2006

2005
A scheduling algorithm for optimization and early planning in high-level synthesis.
ACM Trans. Design Autom. Electr. Syst., 2005

Exploring the limits of leakage power reduction in caches.
ACM Trans. Archit. Code Optim., 2005

Algorithm/Architecture Co-exploration for Designing Energy Efficient Wireless Channel Estimator.
J. Low Power Electron., 2005

Energy Efficient Hardware Synthesis of Polynomial Expressions.
Proceedings of the 18th International Conference on VLSI Design (VLSI Design 2005), 2005

Efficient distributed algorithms for data fusion and node localization in mobile ad-hoc networks.
Proceedings of the IEEE 2nd International Conference on Mobile Adhoc and Sensor Systems, 2005

Storage assignment during high-level synthesis for configurable architectures.
Proceedings of the 2005 International Conference on Computer-Aided Design, 2005

On the Limits of Leakage Power Reduction in Caches.
Proceedings of the 11th International Conference on High-Performance Computer Architecture (HPCA-11 2005), 2005

Instruction scheduling using <i>MAX-MIN</i> ant system optimization.
Proceedings of the 15th ACM Great Lakes Symposium on VLSI 2005, 2005

HARP: hard-wired routing pattern FPGAs.
Proceedings of the ACM/SIGDA 13th International Symposium on Field Programmable Gate Arrays, 2005

Data Partitioning and Optimizations for Reconfigurable Architectures.
Proceedings of The 2005 International Conference on Engineering of Reconfigurable Systems and Algorithms, 2005

MP core: algorithm and design techniques for efficient channel estimation in wireless applications.
Proceedings of the 42nd Design Automation Conference, 2005

Reducing hardware complexity of linear DSP systems by iteratively eliminating two-term common subexpressions.
Proceedings of the 2005 Conference on Asia South Pacific Design Automation, 2005

2004
Timing driven gate duplication.
IEEE Trans. Very Large Scale Integr. Syst., 2004

Factoring and eliminating common subexpressions in polynomial expressions.
Proceedings of the 2004 International Conference on Computer-Aided Design, 2004

A High Performance Application Representation for Reconfigurable Systems.
Proceedings of the International Conference on Engineering of Reconfigurable Systems and Algorithms, 2004

Common Subexpression Elimination Involving Multiple Variables for Linear DSP Synthesis.
Proceedings of the 15th IEEE International Conference on Application-Specific Systems, 2004

2003
Congestion reduction during placement with provably good approximation bound.
ACM Trans. Design Autom. Electr. Syst., 2003

Creating and exploiting flexibility in rectilinear Steiner trees.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2003

Data communication estimation and reduction for reconfigurable systems.
Proceedings of the 40th Design Automation Conference, 2003

2002
Instruction generation for hybrid reconfigurable systems.
ACM Trans. Design Autom. Electr. Syst., 2002

Congestion estimation during top-down placement.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2002

Pattern routing: use and theory for increasing predictability andavoiding coupling.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2002

On the Sensitivity of Incremental Algorithms for Combinatorial Auctions.
Proceedings of the Fourth IEEE International Workshop on Advanced Issues of E-Commerce and Web-Based Information Systems (WECWIS'02), 2002

Instruction generation and regularity extraction for reconfigurable processors.
Proceedings of the International Conference on Compilers, 2002

2001
On the complexity of gate duplication.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2001

Design and analysis of physical design algorithms.
Proceedings of the 2001 International Symposium on Physical Design, 2001

An exact algorithm for coupling-free routing.
Proceedings of the 2001 International Symposium on Physical Design, 2001

Congestion Reduction During Placement Based on Integer Programming.
Proceedings of the 2001 IEEE/ACM International Conference on Computer-Aided Design, 2001

A Super-Scheduler for Embedded Reconfigurable Systems.
Proceedings of the 2001 IEEE/ACM International Conference on Computer-Aided Design, 2001

Instruction Generation for Hybrid Reconfigurable Systems.
Proceedings of the 2001 IEEE/ACM International Conference on Computer-Aided Design, 2001

Creating and Exploiting Flexibility in Steiner Trees.
Proceedings of the 38th Design Automation Conference, 2001

2000
Fast Template Placement for Reconfigurable Computing Systems.
IEEE Des. Test Comput., 2000

3-D Floorplanning: Simulated Annealing and Greedy Placement Methods for Reconfigurable Computing Systems.
Des. Autom. Embed. Syst., 2000

Timing Driven Gate Duplication: Complexity Issues and Algorithms.
Proceedings of the 2000 IEEE/ACM International Conference on Computer-Aided Design, 2000

Predictable Routing.
Proceedings of the 2000 IEEE/ACM International Conference on Computer-Aided Design, 2000

A C to Hardware/Software Compiler.
Proceedings of the 8th IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM 2000), 2000


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