Ryan Gary Kim

Orcid: 0000-0001-9249-3292

According to our database1, Ryan Gary Kim authored at least 36 papers between 2014 and 2023.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Bibliography

2023
AdEle+: An Adaptive Congestion-and-Energy-Aware Elevator Selection for Partially Connected 3D Networks-on-Chip.
IEEE Trans. Computers, August, 2023

RISA: Round-Robin Intra-Rack Friendly Scheduling Algorithm for Disaggregated Datacenters.
Proceedings of the SC '23 Workshops of The International Conference on High Performance Computing, 2023

MOELA: A Multi-Objective Evolutionary/Learning Design Space Exploration Framework for 3D Heterogeneous Manycore Platforms.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2023

2022
RACE: A Reinforcement Learning Framework for Improved Adaptive Control of NoC Channel Buffers.
Proceedings of the GLSVLSI '22: Great Lakes Symposium on VLSI 2022, Irvine CA USA, June 6, 2022

2021
HeM3D: Heterogeneous Manycore Architecture Based on Monolithic 3D Vertical Integration.
ACM Trans. Design Autom. Electr. Syst., 2021

Power Management of Monolithic 3D Manycore Chips with Inter-tier Process Variations.
ACM J. Emerg. Technol. Comput. Syst., 2021

AdEle: An Adaptive Congestion-and-Energy-Aware Elevator Selection for Partially Connected 3D NoCs.
Proceedings of the 58th ACM/IEEE Design Automation Conference, 2021

2020
Inter-Tier Process-Variation-Aware Monolithic 3-D NoC Design Space Exploration.
IEEE Trans. Very Large Scale Integr. Syst., 2020

A Survey of Resource Management for Processing-in-Memory and Near-Memory Processing Architectures.
CoRR, 2020

Learning-Enabled NoC Design for Heterogeneous Manycore Systems.
Proceedings of the 21st International Symposium on Quality Electronic Design, 2020

Power, Performance, and Thermal Trade-offs in M3D-enabled Manycore Chips.
Proceedings of the 2020 Design, Automation & Test in Europe Conference & Exhibition, 2020

2019
Learning-Based Application-Agnostic 3D NoC Design for Heterogeneous Manycore Systems.
IEEE Trans. Computers, 2019

Inter-Tier Process Variation-Aware Monolithic 3D NoC Architectures.
CoRR, 2019

Learning-Based Design Space Exploration of Emerging 3D NoC Architectures.
Proceedings of the Tenth International Green and Sustainable Computing Conference, 2019

Design and Optimization of Heterogeneous Manycore Systems Enabled by Emerging Interconnect Technologies: Promises and Challenges.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2019

2018
On-Chip Communication Network for Efficient Training of Deep Convolutional Networks on Heterogeneous Manycore Systems.
IEEE Trans. Computers, 2018

Machine Learning and Manycore Systems Design: A Serendipitous Symbiosis.
Computer, 2018

Machine learning for design space exploration and optimization of manycore systems.
Proceedings of the International Conference on Computer-Aided Design, 2018

2017
Imitation Learning for Dynamic VFI Control in Large-Scale Manycore Systems.
IEEE Trans. Very Large Scale Integr. Syst., 2017

A Sub-cm<sup>3</sup> Energy-Harvesting Stacked Wireless Sensor Node Featuring a Near-Threshold Voltage IA-32 Microcontroller in 14-nm Tri-Gate CMOS for Always-ON Always-Sensing Applications.
IEEE J. Solid State Circuits, 2017

3D NoC-Enabled Heterogeneous Manycore Architectures for Accelerating CNN Training: Performance and Thermal Trade-offs.
Proceedings of the Eleventh IEEE/ACM International Symposium on Networks-on-Chip, 2017

Adaptive Manycore Architectures for Big Data Computing.
Proceedings of the Eleventh IEEE/ACM International Symposium on Networks-on-Chip, 2017

2016
Wireless NoC and Dynamic VFI Codesign: Energy Efficiency Without Performance Penalty.
IEEE Trans. Very Large Scale Integr. Syst., 2016

Wireless NoC for VFI-Enabled Multicore Chip Design: Performance Evaluation and Design Trade-Offs.
IEEE Trans. Computers, 2016

An energy harvesting wireless sensor node for IoT systems featuring a near-threshold voltage IA-32 microcontroller in 14nm tri-gate CMOS.
Proceedings of the 2016 IEEE Symposium on VLSI Circuits, 2016

Hybrid network-on-chip architectures for accelerating deep learning kernels on heterogeneous manycore platforms.
Proceedings of the 2016 International Conference on Compilers, 2016

2015
Improving EDP in wireless NoC-enabled multicore chips via DVFS pruning.
Proceedings of the IEEE 58th International Midwest Symposium on Circuits and Systems, 2015

Enhancing performance of wireless NoCs with distributed MAC protocols.
Proceedings of the Sixteenth International Symposium on Quality Electronic Design, 2015

The (Low) Power of Less Wiring: Enabling Energy Efficiency in Many-Core Platforms Through Wireless NoC.
Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2015

Energy efficient MapReduce with VFI-enabled multicore platforms.
Proceedings of the 52nd Annual Design Automation Conference, 2015

2014
Design Space Exploration for Wireless NoCs Incorporating Irregular Network Routing.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2014

Performance Evaluation of Congestion-Aware Routing with DVFS on a Millimeter-Wave Small-World Wireless NoC.
ACM J. Emerg. Technol. Comput. Syst., 2014

An energy-efficient millimeter-wave wireless NoC with congestion-aware routing and DVFS.
Proceedings of the Eighth IEEE/ACM International Symposium on Networks-on-Chip, 2014

Thermal hotspot reduction in mm-Wave wireless NoC architectures.
Proceedings of the Fifteenth International Symposium on Quality Electronic Design, 2014

Performance evaluation of wireless NoCs in presence of irregular network routing strategies.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014

Energy-efficient VFI-partitioned multicore design using wireless NoC architectures.
Proceedings of the 2014 International Conference on Compilers, 2014


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