Russell Tessier

Proceedings of the 30th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2022

2021

LifeLine for FPGA Protection: Obfuscated Cryptography for Real-World Security.

[BibT_eX]

[DOI]

IACR Trans. Cryptogr. Hardw. Embed. Syst., 2021

On the Design and Misuse of Microcoded (Embedded) Processors - A Cautionary Note.

[BibT_eX]

[DOI]

IACR Cryptol. ePrint Arch., 2021

Power Side-Channel Attacks on BNN Accelerators in Remote FPGAs.

[BibT_eX]

[DOI]

IEEE J. Emerg. Sel. Topics Circuits Syst., 2021

Remote Power Attacks on the Versatile Tensor Accelerator in Multi-Tenant FPGAs.

[BibT_eX]

[DOI]

Proceedings of the 29th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2021

Remote Power Side-Channel Attacks on BNN Accelerators in FPGAs.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2021

2020

Power Distribution Attacks in Multitenant FPGAs.

[BibT_eX]

[DOI]

George Provelengios

IEEE Trans. Very Large Scale Integr. Syst., 2020

CoNFV: A Heterogeneous Platform for Scalable Network Function Virtualization.

[BibT_eX]

[DOI]

ACM Trans. Reconfigurable Technol. Syst., 2020

Remote Power Side-Channel Attacks on CNN Accelerators in FPGAs.

[BibT_eX]

[DOI]

CoRR, 2020

NestedNet: A Container-based Prototyping Tool for Hierarchical Software Defined Networks.

[BibT_eX]

[DOI]

Xuzhi Zhang

Narendra Prabhu

Proceedings of the International Workshop on Rapid System Prototyping, 2020

Understanding and Comparing the Capabilities of On-Chip Voltage Sensors against Remote Power Attacks on FPGAs.

[BibT_eX]

[DOI]

Proceedings of the 63rd IEEE International Midwest Symposium on Circuits and Systems, 2020

Service Chaining for Heterogeneous Middleboxes.

[BibT_eX]

[DOI]

Xuzhi Zhang

Proceedings of the International Conference on Field-Programmable Technology, 2020

Jitter-based Adaptive True Random Number Generation for FPGAs in the Cloud.

[BibT_eX]

[DOI]

Proceedings of the International Conference on Field-Programmable Technology, 2020

Power Wasting Circuits for Cloud FPGA Attacks.

[BibT_eX]

[DOI]

George Provelengios

Proceedings of the 30th International Conference on Field-Programmable Logic and Applications, 2020

2019

Efficient PUF-Based Key Generation in FPGAs Using Per-Device Configuration.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2019

Loop Unrolling for Energy Efficiency in Low-Cost Field-Programmable Gate Arrays.

[BibT_eX]

[DOI]

ACM Trans. Reconfigurable Technol. Syst., 2019

Introduction to the Special Section on Security in FPGA-accelerated Cloud and Datacenters.

[BibT_eX]

[DOI]

ACM Trans. Reconfigurable Technol. Syst., 2019

HAL - The Missing Piece of the Puzzle for Hardware Reverse Engineering, Trojan Detection and Insertion.

[BibT_eX]

[DOI]

IEEE Trans. Dependable Secur. Comput., 2019

Closed-Loop Proportion-Derivative Control of Suppressing Seizures in a Neural Mass Model.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2019

Characterizing Power Distribution Attacks in Multi-User FPGA Environments.

[BibT_eX]

[DOI]

George Provelengios

Proceedings of the 29th International Conference on Field Programmable Logic and Applications, 2019

Characterization of Long Wire Data Leakage in Deep Submicron FPGAs.

[BibT_eX]

[DOI]

Proceedings of the 2019 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2019

2018

On the Difficulty of FSM-based Hardware Obfuscation.

[BibT_eX]

[DOI]

IACR Trans. Cryptogr. Hardw. Embed. Syst., 2018

Hybrid Obfuscation to Protect Against Disclosure Attacks on Embedded Microprocessors.

[BibT_eX]

[DOI]

IEEE Trans. Computers, 2018

A Hardware Monitor to Protect Linux System Calls.

[BibT_eX]

[DOI]

Proceedings of the 2018 IEEE Computer Society Annual Symposium on VLSI, 2018

Lynq: A Lightweight Software Layer for Rapid SoC FPGA Prototyping.

[BibT_eX]

[DOI]

Proceedings of the 28th International Conference on Field Programmable Logic and Applications, 2018

FPGA Side Channel Attacks without Physical Access.

[BibT_eX]

[DOI]

Chethan Ramesh

Shivukumar B. Patil

Siva Nishok Dhanuskodi

Proceedings of the 26th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2018

A Bandwidth-Optimized Routing Algorithm for Hybrid FPGA Networks-on-Chip.

[BibT_eX]

[DOI]

Shivukumar B. Patil

Tianqi Liu

Proceedings of the 26th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2018

2017

A High-Speed Accelerator for Homomorphic Encryption using the Karatsuba Algorithm.

[BibT_eX]

[DOI]

ACM Trans. Embed. Comput. Syst., 2017

Scalable Network Function Virtualization for Heterogeneous Middleboxes.

[BibT_eX]

[DOI]

Proceedings of the 25th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2017

Energy Efficient Loop Unrolling for Low-Cost FPGAs.

[BibT_eX]

[DOI]

Proceedings of the 25th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2017

Hardware support for embedded operating system security.

[BibT_eX]

[DOI]

Arman Pouraghily

Harikrishnan Kumarapillai Chandrikakutty

Proceedings of the 28th IEEE International Conference on Application-specific Systems, 2017

2016

Dynamic Hardware Monitors for Network Processor Protection.

[BibT_eX]

[DOI]

Kekai Hu

Zachary Goodman

IEEE Trans. Computers, 2016

Soft GPGPUs for Embedded FPGAs: An Architectural Evaluation.

[BibT_eX]

[DOI]

Kevin Andryc

Tedy Thomas

CoRR, 2016

Hybrid hard NoCs for efficient FPGA communication.

[BibT_eX]

[DOI]

Tianqi Liu

Naveen Kumar Dumpala

Proceedings of the 2016 International Conference on Field-Programmable Technology, 2016

Improving the efficiency of PUF-based key generation in FPGAs using variation-aware placement.

[BibT_eX]

[DOI]

Proceedings of the 26th International Conference on Field Programmable Logic and Applications, 2016

Effects of I/O routing through column interfaces in embedded FPGA fabrics.

[BibT_eX]

[DOI]

Christophe Huriaux

Olivier Sentieys

Proceedings of the 26th International Conference on Field Programmable Logic and Applications, 2016

2015

Securing Network Processors with High-Performance Hardware Monitors.

[BibT_eX]

[DOI]

Harikrishnan Kumarapillai Chandrikakutty

Kekai Hu

IEEE Trans. Dependable Secur. Comput., 2015

Reconfigurable Computing Architectures.

[BibT_eX]

[DOI]

Kenneth L. Pocek

André DeHon

Proc. IEEE, 2015

Reinforcement Learning for Thermal-aware Many-core Task Allocation.

[BibT_eX]

[DOI]

Proceedings of the 25th edition on Great Lakes Symposium on VLSI, GLVLSI 2015, Pittsburgh, PA, USA, May 20, 2015

Adaptive MRAM-based CGRAs.

[BibT_eX]

[DOI]

Proceedings of the 25th International Conference on Field Programmable Logic and Applications, 2015

Protecting against Cryptographic Trojans in FPGAs.

[BibT_eX]

[DOI]

Proceedings of the 23rd IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2015

Hardware-assisted code obfuscation for FPGA soft microprocessors.

[BibT_eX]

[DOI]

Meha Kainth

Lekshmi Krishnan

Chaitra Narayana

Sandesh Gubbi Virupaksha

Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015

Multi-task support for security-enabled embedded processors.

[BibT_eX]

[DOI]

Proceedings of the 26th IEEE International Conference on Application-specific Systems, 2015

2014

Dynamic On-Chip Thermal Sensor Calibration Using Performance Counters.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2014

A Broadcast-Enabled Sensing System for Embedded Multi-core Processors.

[BibT_eX]

[DOI]

Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2014

FPGA architecture support for heterogeneous, relocatable partial bitstreams.

[BibT_eX]

[DOI]

Christophe Huriaux

Olivier Sentieys

Proceedings of the 24th International Conference on Field Programmable Logic and Applications, 2014

FPGA Architecture Enhancements to Support Heterogeneous Partially Reconfigurable Regions.

[BibT_eX]

[DOI]

Christophe Huriaux

Olivier Sentieys

Proceedings of the 22nd IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2014

System-Level Security for Network Processors with Hardware Monitors.

[BibT_eX]

[DOI]

Proceedings of the 51st Annual Design Automation Conference 2014, 2014

2013

Configurable memory security in embedded systems.

[BibT_eX]

[DOI]

ACM Trans. Embed. Comput. Syst., 2013

Reconfigurable Data Planes for Scalable Network Virtualization.

[BibT_eX]

[DOI]

IEEE Trans. Computers, 2013

Real-Time Differential Signal Phase Estimation for Space-Based Systems using FPGAs.

[BibT_eX]

[DOI]

Paul Siqueira

Vishwas Vijayendra

IEEE Trans. Aerosp. Electron. Syst., 2013

Accelerating iterative algorithms with asynchronous accumulative updates on FPGAs.

[BibT_eX]

[DOI]

Sandesh Gubbi Virupaksha

Lekshmi Krishnan

Lixin Gao

Proceedings of the 2013 International Conference on Field-Programmable Technology, 2013

An open-source SATA core for Virtex-4 FPGAs.

[BibT_eX]

[DOI]

Cory Gorman

Paul Siqueira

Proceedings of the 2013 International Conference on Field-Programmable Technology, 2013

FlexGrip: A soft GPGPU for FPGAs.

[BibT_eX]

[DOI]

Kevin Andryc

Murtaza Merchant

Proceedings of the 2013 International Conference on Field-Programmable Technology, 2013

Run-time probabilistic detection of miscalibrated thermal sensors in many-core systems.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation and Test in Europe, 2013

FPGA latency optimization using system-level transformations and DFG restructuring.

[BibT_eX]

[DOI]

Daniel Gomez-Prado

Maciej J. Ciesielski

Proceedings of the Design, Automation and Test in Europe, 2013

High-performance hardware monitors to protect network processors from data plane attacks.

[BibT_eX]

[DOI]

Proceedings of the 50th Annual Design Automation Conference 2013, 2013

Scalable hardware monitors to protect network processors from data plane attacks.

[BibT_eX]

[DOI]

Kekai Hu

Proceedings of the IEEE Conference on Communications and Network Security, 2013

2012

Collaborative calibration of on-chip thermal sensors using performance counters.

[BibT_eX]

[DOI]

Proceedings of the 2012 IEEE/ACM International Conference on Computer-Aided Design, 2012

Saving energy and improving TCP throughput with rate adaptation in Ethernet.

[BibT_eX]

[DOI]

Proceedings of IEEE International Conference on Communications, 2012

Distributed sensor data processing for many-cores.

[BibT_eX]

[DOI]

Proceedings of the Great Lakes Symposium on VLSI 2012, 2012

2011

A Dedicated Monitoring Infrastructure for Multicore Processors.

[BibT_eX]

[DOI]

Sailaja Madduri

IEEE Trans. Very Large Scale Integr. Syst., 2011

Securing the data path of next-generation router systems.

[BibT_eX]

[DOI]

Gayatri Prabhu

Comput. Commun., 2011

Customizing virtual networks with partial FPGA reconfiguration.

[BibT_eX]

[DOI]

Comput. Commun. Rev., 2011

Evaluation of the Universal Geocast Scheme for VANETs.

[BibT_eX]

[DOI]

Proceedings of the 74th IEEE Vehicular Technology Conference, 2011

Efficient key-dependent message authentication in reconfigurable hardware.

[BibT_eX]

[DOI]

Proceedings of the 2011 International Conference on Field-Programmable Technology, 2011

A Dynamically-Reconfigurable Phased Array Radar Processing System.

[BibT_eX]

[DOI]

Proceedings of the International Conference on Field Programmable Logic and Applications, 2011

ReClick - A Modular Dataplane Design Framework for FPGA-Based Network Virtualization.

[BibT_eX]

[DOI]

Proceedings of the 2011 ACM/IEEE Symposium on Architectures for Networking and Communications Systems (ANCS), 2011

Real-time estimates of differential signal phase for spaceborne systems using FPGAs.

[BibT_eX]

[DOI]

Vishwas Vijayendra

Paul Siqueira

Akilesh Krishnamurthy

Proceedings of the 2011 NASA/ESA Conference on Adaptive Hardware and Systems, 2011

2010

Thermal-aware voltage droop compensation for multi-core architectures.

[BibT_eX]

[DOI]

Proceedings of the 20th ACM Great Lakes Symposium on VLSI 2009, 2010

Scalable network virtualization using FPGAs.

[BibT_eX]

[DOI]

Proceedings of the ACM/SIGDA 18th International Symposium on Field Programmable Gate Arrays, 2010

Reconfigurable Sparse Matrix-Vector Multiplication on FPGAs.

[BibT_eX]

Salma Mirza

J. Blair Perot

Proceedings of the 2010 International Conference on Engineering of Reconfigurable Systems & Algorithms, 2010

Multicore soft error rate stabilization using adaptive dual modular redundancy.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation and Test in Europe, 2010

2009

Tetris-XL: A performance-driven spill reduction technique for embedded VLIW processors.

[BibT_eX]

[DOI]

Eduardo Braulio Wanderley Netto

ACM Trans. Archit. Code Optim., 2009

A security approach for off-chip memory in embedded microprocessor systems.

[BibT_eX]

[DOI]

Romain Vaslin

Guy Gogniat

Jean-Philippe Diguet

Microprocess. Microsystems, 2009

An Interactive Approach to Timing Accurate PCI-X Simulation.

[BibT_eX]

[DOI]

Kevin Andryc

Patrick Kelly

Proceedings of the Twentienth IEEE/IFIP International Symposium on Rapid System Prototyping, 2009

Design of a Secure Router System for Next-Generation Networks.

[BibT_eX]

[DOI]

Proceedings of the Third International Conference on Network and System Security, 2009

CMOS vs Nano: comrades or rivals?

[BibT_eX]

[DOI]

Proceedings of the ACM/SIGDA 17th International Symposium on Field Programmable Gate Arrays, 2009

Application Specific Customization and Scalability of Soft Multiprocessors.

[BibT_eX]

[DOI]

Proceedings of the FCCM 2009, 2009

A monitor interconnect and support subsystem for multicore processors.

[BibT_eX]

[DOI]

Sailaja Madduri

Proceedings of the Design, Automation and Test in Europe, 2009

2008

Memory security management for reconfigurable embedded systems.

[BibT_eX]

[DOI]

Proceedings of the 2008 International Conference on Field-Programmable Technology, 2008

2007

Power-Efficient RAM Mapping Algorithms for FPGA Embedded Memory Blocks.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2007

FPGA Architecture: Survey and Challenges.

[BibT_eX]

[DOI]

Ian Kuon

Eduardo Braulio Wanderley Netto

Jonathan Rose

Found. Trends Electron. Des. Autom., 2007

Low latency Solution for Confidentiality and Integrity Checking in Embedded Systems with Off-Chip Memory.

[BibT_eX]

Romain Vaslin

Guy Gogniat

Proceedings of the 3rd International Workshop on Reconfigurable Communication-centric Systems-on-Chip, 2007

Tetris: a new register pressure control technique for VLIW processors.

[BibT_eX]

[DOI]

Proceedings of the 2007 ACM SIGPLAN/SIGBED Conference on Languages, 2007

Power-aware FPGA logic synthesis using binary decision diagrams.

[BibT_eX]

[DOI]

Kevin Oo Tinmaung

David Howland

Proceedings of the ACM/SIGDA 15th International Symposium on Field Programmable Gate Arrays, 2007

Establishing Chain of Trust in Reconfigurable Hardware.

[BibT_eX]

[DOI]

Proceedings of the IEEE Symposium on Field-Programmable Custom Computing Machines, 2007

High-efficiency protection solution for off-chip memory in embedded systems.

[BibT_eX]

Proceedings of the 2007 International Conference on Engineering of Reconfigurable Systems & Algorithms, 2007

2006

Design-specific path delay testing in lookup-table-based FPGAs.

[BibT_eX]

[DOI]

Premachandran R. Menon

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2006

Field-Programmable Gate Arrays in Embedded Systems.

[BibT_eX]

[DOI]

Miriam Leeser

Scott Hauck

Venkatachalam Chandrasekar

EURASIP J. Embed. Syst., 2006

Power-aware RAM mapping for FPGA embedded memory blocks.

[BibT_eX]

[DOI]

Proceedings of the ACM/SIGDA 14th International Symposium on Field Programmable Gate Arrays, 2006

An adaptive Reed-Solomon errors-and-erasures decoder.

[BibT_eX]

[DOI]

Proceedings of the ACM/SIGDA 14th International Symposium on Field Programmable Gate Arrays, 2006

2005

A reconfigurable, power-efficient adaptive Viterbi decoder.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2005

An energy-aware active smart card.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2005

Salient features of radar nodes of the first generation NetRad System.

[BibT_eX]

[DOI]

Francesc Junyent

Proceedings of the IEEE International Geoscience & Remote Sensing Symposium, 2005

2004

Guest Editorial: Field Programmable Logic.

[BibT_eX]

[DOI]

Roger F. Woods

J. VLSI Signal Process., 2004

Dynamically Parameterized Algorithms and Architectures to Exploit Signal Variations.

[BibT_eX]

[DOI]

J. VLSI Signal Process., 2004

Trading off transient fault tolerance and power consumption in deep submicron (DSM) VLSI circuits.

[BibT_eX]

[DOI]

Atul Maheshwari

IEEE Trans. Very Large Scale Integr. Syst., 2004

An architecture and compiler for scalable on-chip communication.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2004

A pod-based dual-beam SAR.

[BibT_eX]

[DOI]

IEEE Geosci. Remote. Sens. Lett., 2004

A Dynamically-Reconfigurable, Power-Efficient Turbo Decoder.

[BibT_eX]

[DOI]

Jian Liang

Dennis Goeckel

Proceedings of the 12th IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM 2004), 2004

2003

Technology mapping algorithms for hybrid FPGAs containing lookup tables and PLAs.

[BibT_eX]

[DOI]

Srini Krishnamoorthy

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2003

First observations with the UMass dual-beam InSAR.

[BibT_eX]

[DOI]

Proceedings of the 2003 IEEE International Geoscience and Remote Sensing Symposium, 2003

Adaptive system on a chip (ASOC): a backbone for power-aware signal processing cores.

[BibT_eX]

[DOI]

Proceedings of the 2003 International Conference on Image Processing, 2003

A hybrid adiabatic content addressable memory for ultra low-power applications.

[BibT_eX]

[DOI]

Proceedings of the 13th ACM Great Lakes Symposium on VLSI 2003, 2003

Adaptive Fault Recovery for Networked Reconfigurable Systems.

[BibT_eX]

[DOI]

Ramshankar Ramanarayanan

Proceedings of the 11th IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM 2003), 2003

Floating Point Unit Generation and Evaluation for FPGAs.

[BibT_eX]

[DOI]

Jian Liang

Oskar Mencer

Proceedings of the 11th IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM 2003), 2003

2002

Incremental compilation for parallel logic verification systems.

[BibT_eX]

[DOI]

Snigdha Jana

IEEE Trans. Very Large Scale Integr. Syst., 2002

BDD-based logic synthesis for LUT-based FPGAs.

[BibT_eX]

[DOI]

Navin Vemuri

Priyank Kalla

ACM Trans. Design Autom. Electr. Syst., 2002

Fast placement approaches for FPGAs.

[BibT_eX]

[DOI]

ACM Trans. Design Autom. Electr. Syst., 2002

Static scheduling of multidomain circuits for fast functional verification.

[BibT_eX]

[DOI]

Murali Kudlugi

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2002

Testing and diagnosis of interconnect faults in cluster-based FPGA architectures.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2002

Trading off Reliability and Power-Consumption in Ultra-low Power Systems.

[BibT_eX]

[DOI]

Atul Maheshwari

Proceedings of the 3rd International Symposium on Quality of Electronic Design, 2002

The Integration of SystemC and Hardware-Assisted Verification.

[BibT_eX]

[DOI]

Ramaswamy Ramaswamy

Proceedings of the Field-Programmable Logic and Applications, 2002

A dynamically reconfigurable adaptive viterbi decoder.

[BibT_eX]

[DOI]

Proceedings of the ACM/SIGDA International Symposium on Field Programmable Gate Arrays, 2002

2001

Reconfigurable Computing for Digital Signal Processing: A Survey.

[BibT_eX]

[DOI]

J. VLSI Signal Process., 2001

BIST-based delay path testing in FPGA architectures.

[BibT_eX]

[DOI]

Premachandran R. Menon

Proceedings of the Proceedings IEEE International Test Conference 2001, Baltimore, MD, USA, 30 October, 2001

Static Scheduling of Multi-Domain Memories For Functional Verification.

[BibT_eX]

[DOI]

Murali Kudlugi

Charles Selvidge

Proceedings of the 2001 IEEE/ACM International Conference on Computer-Aided Design, 2001

Dynamically parameterized algorithms and architectures to exploit signal variations for improved performance and reduced power.

[BibT_eX]

[DOI]

Subramanian Venkatraman

Vidhya Thyagarajan

Proceedings of the IEEE International Conference on Acoustics, 2001

Static Scheduling of Multiple Asynchronous Domains For Functional Verification.

[BibT_eX]

[DOI]

Murali Kudlugi

Charles Selvidge

Proceedings of the 38th Design Automation Conference, 2001

2000

Diagnosis of Interconnect Faults in Cluster-Based FPGA Architectures.

[BibT_eX]

[DOI]

Proceedings of the 2000 IEEE/ACM International Conference on Computer-Aided Design, 2000

Balancing Logic Utilization and Area Efficiency in FPGAs.

[BibT_eX]

[DOI]

Heather Giza

Proceedings of the Field-Programmable Logic and Applications, 2000

Area-Optimized Technology Mapping for Hybrid FPGAs.

[BibT_eX]

[DOI]

Srini Krishnamoorthy

Sriram Swaminathan

Proceedings of the Field-Programmable Logic and Applications, 2000

Tolerating operational faults in cluster-based FPGAs.

[BibT_eX]

[DOI]

Vijay Lakamraju

Proceedings of the ACM/SIGDA International Symposium on Field Programmable Gate Arrays, 2000

Interconnect testing in cluster-based FPGA architectures.

[BibT_eX]

[DOI]

Proceedings of the 37th Conference on Design Automation, 2000

aSOC: A Scalable, Single-Chip Communications Architecture.

[BibT_eX]

[DOI]

Jian Liang

Sriram Swaminathan

Proceedings of the 2000 International Conference on Parallel Architectures and Compilation Techniques (PACT'00), 2000

1999

Fast place and route approaches for field-programmable gate arrays.

[BibT_eX]

[DOI]

PhD thesis, 1999

Incremental Compilation for Logic Emulation.

[BibT_eX]

[DOI]

Proceedings of the Tenth IEEE International Workshop on Rapid System Prototyping (RSP 1999), 1999

Frontier: A Fast Placement System for FPGAs.

[BibT_eX]