Russ Joseph
Orcid: 0000-0001-6349-1888Affiliations:
- Northwestern University, Evanston, IL, USA
According to our database1,
Russ Joseph
authored at least 34 papers
between 2001 and 2020.
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Bibliography
2020
An Adaptive Clock Scheme Exploiting Instruction-Based Dynamic Timing Slack for a GPGPU Architecture.
IEEE J. Solid State Circuits, 2020
NCPU: An Embedded Neural CPU Architecture on Resource-Constrained Low Power Devices for Real-time End-to-End Performance.
Proceedings of the 53rd Annual IEEE/ACM International Symposium on Microarchitecture, 2020
2019
An Instruction-Driven Adaptive Clock Management Through Dynamic Phase Scaling and Compiler Assistance for a Low Power Microprocessor.
IEEE J. Solid State Circuits, 2019
An Adaptive Clock Management Scheme Exploiting Instruction-Based Dynamic Timing Slack for a General-Purpose Graphics Processor Unit with Deep Pipeline and Out-of-Order Execution.
Proceedings of the IEEE International Solid- State Circuits Conference, 2019
Proceedings of the 46th International Symposium on Computer Architecture, 2019
2018
Cocoa: synergistic cache compression and error correction in capacity sensitive last level caches.
Proceedings of the International Symposium on Memory Systems, 2018
An Instruction Driven Adaptive Clock Phase Scaling with Timing Encoding and Online Instruction Calibration for a Low Power Microprocessor.
Proceedings of the 44th IEEE European Solid State Circuits Conference, 2018
Compiler-guided instruction-level clock scheduling for timing speculative processors.
Proceedings of the 55th Annual Design Automation Conference, 2018
2017
D2M: data-driven model for fast and accurate timing error simulation in statically scheduled microprocessors.
Proceedings of the Summer Simulation Multi-Conference, 2017
(Invited) Software-guided greybox design methodology with integrated power and clock management.
Proceedings of the IEEE 60th International Midwest Symposium on Circuits and Systems, 2017
Greybox Design Methodology: A Program Driven Hardware Co-optimization with Ultra-Dynamic Clock Management.
Proceedings of the 54th Annual Design Automation Conference, 2017
2016
Proceedings of the 46th Annual IEEE/IFIP International Conference on Dependable Systems and Networks, 2016
Exploration of associative power management with instruction governed operation for ultra-low power design.
Proceedings of the 53rd Annual Design Automation Conference, 2016
2015
Proceedings of the 2015 International Conference on Compilers, 2015
2012
IEEE Trans. Very Large Scale Integr. Syst., 2012
Virtual-machine-based emulation of future generation high-performance computing systems.
Int. J. High Perform. Comput. Appl., 2012
Spatially- and temporally-adaptive communication protocols for zero-maintenance sensor networks relying on opportunistic energy scavenging.
Proceedings of the 10th International Conference on Hardware/Software Codesign and System Synthesis, 2012
2011
Proceedings of the 44rd Annual IEEE/ACM International Symposium on Microarchitecture, 2011
Proceedings of the Design, Automation and Test in Europe, 2011
Proceedings of the 16th International Conference on Architectural Support for Programming Languages and Operating Systems, 2011
2010
IEEE Comput. Archit. Lett., 2010
2009
IEEE Comput. Archit. Lett., 2009
Proceedings of the 46th Design Automation Conference, 2009
2008
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2008
Proceedings of the 17th International Conference on Parallel Architectures and Compilation Techniques, 2008
2007
IEEE Micro, 2007
Proceedings of the 2007 IEEE International Symposium on Performance Analysis of Systems and Software, 2007
Understanding voltage variations in chip multiprocessors using a distributed power-delivery network.
Proceedings of the 2007 Design, Automation and Test in Europe Conference and Exposition, 2007
Power deregulation: eliminating off-chip voltage regulation circuitry from embedded systems.
Proceedings of the 5th International Conference on Hardware/Software Codesign and System Synthesis, 2007
2006
Proceedings of the 2006 International Symposium on Low Power Electronics and Design, 2006
2004
Proceedings of the 2004 IEEE International Symposium on Performance Analysis of Systems and Software, 2004
Wavelet Analysis for Microprocessor Design: Experiences with Wavelet-Based dI/dt Characterization.
Proceedings of the 10th International Conference on High-Performance Computer Architecture (HPCA-10 2004), 2004
2003
Proceedings of the Ninth International Symposium on High-Performance Computer Architecture (HPCA'03), 2003
2001
Proceedings of the 2001 International Symposium on Low Power Electronics and Design, 2001