Rushik Parmar
Orcid: 0000-0001-9534-6191
According to our database1,
Rushik Parmar
authored at least 9 papers
between 2022 and 2024.
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Collaborative distances:
Timeline
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2023
2024
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Book In proceedings Article PhD thesis Dataset OtherLinks
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Bibliography
2024
A Low-Power Co-Processor to Predict Ventricular Arrhythmia for Wearable Healthcare Devices.
IEEE Trans. Very Large Scale Integr. Syst., September, 2024
An SNN-Inspired Area- and Power-Efficient VLSI Architecture of Myocardial Infarction Classifier for Wearable Devices.
IEEE Trans. Circuits Syst. II Express Briefs, June, 2024
Reprogrammable Time-Domain RRAM Based Vector Matrix Multiplier for In-Memory Computing.
Proceedings of the 25th International Symposium on Quality Electronic Design, 2024
2023
Design of DNN-Based Low-Power VLSI Architecture to Classify Atrial Fibrillation for Wearable Devices.
IEEE Trans. Very Large Scale Integr. Syst., March, 2023
MInSC: A VLSI Architecture for Myocardial Infarction Stages Classifier for Wearable Healthcare Applications.
IEEE Trans. Circuits Syst. II Express Briefs, March, 2023
Programmable Binary Weighted Time-Domain Vector Matrix Multiplier for In-Memory Computing.
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2023
2022
A DNN-Based Low Power ECG Co-Processor Architecture to Classify Cardiac Arrhythmia for Wearable Devices.
IEEE Trans. Circuits Syst. II Express Briefs, 2022
An Area and Power Efficient VLSI Architecture to Detect Obstructive Sleep Apnea for Wearable Devices.
Proceedings of the 32nd International Conference Radioelektronika, 2022
An Energy Efficient and Resource Optimal VLSI Architecture for ECG Feature Extraction for Wearable Healthcare Applications.
Proceedings of the 32nd International Conference Radioelektronika, 2022