Rupak Samanta

According to our database1, Rupak Samanta authored at least 7 papers between 2007 and 2010.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

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Article 
PhD thesis 
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Links

On csauthors.net:

Bibliography

2010
Discrete Buffer and Wire Sizing for Link-Based Non-Tree Clock Networks.
IEEE Trans. Very Large Scale Integr. Syst., 2010

2009
Clock Buffer Polarity Assignment for Power Noise Reduction.
IEEE Trans. Very Large Scale Integr. Syst., 2009

2008
Dynamic Aggregation of Virtual Addresses in TLB Using TCAM Cells.
Proceedings of the 21st International Conference on VLSI Design (VLSI Design 2008), 2008

Elastic Timing Scheme for Energy-Efficient and Robust Performance.
Proceedings of the 9th International Symposium on Quality of Electronic Design (ISQED 2008), 2008

Built-In Proactive Tuning System for Circuit Aging Resilience.
Proceedings of the 23rd IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2008), 2008

2007
An Enhanced CAM Architecture to Accelerate LZW Compression Algorithm.
Proceedings of the 20th International Conference on VLSI Design (VLSI Design 2007), 2007

Modeling, optimization and control of rotary traveling-wave oscillator.
Proceedings of the 2007 International Conference on Computer-Aided Design, 2007


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