Ruoyang Liu

According to our database, Ruoyang Liu authored at least 16 papers between 2019 and 2024.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2024

RE-Specter: Examining the Architectural Features of Configurable CNN With Power Side-Channel.

Lu Zhang, Dejun Mu, Jingyu Wang, Ruoyang Liu, Yifan He, Yaolei Li, Yu Tai, Shengbing Zhang, Xiaoya Fan, Huazhong Yang, Yongpan Liu

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., October, 2024

A Dynamic Execution Neural Network Processor for Fine-Grained Mixed-Precision Model Training Based on Online Quantization Sensitivity Analysis.

Ruoyang Liu, Chenhan Wei, Yixiong Yang, Wenxun Wang, Binbin Yuan, Huazhong Yang, Yongpan Liu

IEEE J. Solid State Circuits, September, 2024

Entropy Solutions to the Dirichlet Problem for Nonlinear Diffusion Equations with Conservative Noise.

Kai Du, Ruoyang Liu, Yuxing Wang

SIAM J. Math. Anal., February, 2024

A new feature extraction algorithm for measuring the spatial arrangement of texture Primitives: Distance coding diversity.

Wenquan Zhu, Xinyi Yang, Ruoyang Liu, Cenliang Zhao

Int. J. Appl. Earth Obs. Geoinformation, 2024

2023

Screening Image Features of Collapsed Buildings for Operational and Rapid Remote Sensing Identification.

Ruoyang Liu, Wenquan Zhu, Xinyi Yang

Remote. Sens., December, 2023

A 28nm 1.07TFLOPS/mm² Dynamic-Precision Training Processor with Online Dynamic Execution and Multi- Level-Aligned Block-FP Processing.

Yixiong Yang, Ruoyang Liu, Chenhan Wei, Wenxun Wang, Wenyu Sun, Jinshan Yue, Huazhong Yang, Yongpan Liu

Proceedings of the IEEE Custom Integrated Circuits Conference, 2023

Block-Wise Dynamic-Precision Neural Network Training Acceleration via Online Quantization Sensitivity Analytics.

Ruoyang Liu, Chenhan Wei, Yixiong Yang, Wenxun Wang, Huazhong Yang, Yongpan Liu

Proceedings of the 28th Asia and South Pacific Design Automation Conference, 2023

2022

PACA: A Pattern Pruning Algorithm and Channel-Fused High PE Utilization Accelerator for CNNs.

Jingyu Wang, Songming Yu, Zhuqing Yuan, Jinshan Yue, Zhe Yuan, Ruoyang Liu, Yanzhi Wang, Huazhong Yang, Xueqing Li, Yongpan Liu

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022

A 65-nm Energy-Efficient Interframe Data Reuse Neural Network Accelerator for Video Applications.

Yixiong Yang, Yongpan Liu, Zhe Yuan, Wenyu Sun, Ruoyang Liu, Jingyu Wang, Jinshan Yue, Xiaoyu Feng, Zhuqing Yuan, Xueqing Li, Huazhong Yang

IEEE J. Solid State Circuits, 2022

Toward Low-Bit Neural Network Training Accelerator by Dynamic Group Accumulation.

Yixiong Yang, Ruoyang Liu, Wenyu Sun, Jinshan Yue, Huazhong Yang, Yongpan Liu

Proceedings of the 27th Asia and South Pacific Design Automation Conference, 2022

2021

STICKER-T: An Energy-Efficient Neural Network Processor Using Block-Circulant Algorithm and Unified Frequency-Domain Acceleration.

Jinshan Yue, Yongpan Liu, Ruoyang Liu, Wenyu Sun, Zhe Yuan, Yung-Ning Tu, Yi-Ju Chen, Ao Ren, Yanzhi Wang, Meng-Fan Chang, Xueqing Li, Huazhong Yang

IEEE J. Solid State Circuits, 2021

PETRI: Reducing Bandwidth Requirement in Smart Surveillance by Edge-Cloud Collaborative Adaptive Frame Clustering and Pipelined Bidirectional Tracking.

Ruoyang Liu, Lu Zhang, Jingyu Wang, Huazhong Yang, Yongpan Liu

Proceedings of the 58th ACM/IEEE Design Automation Conference, 2021

2020

GAAS: An Efficient Group Associated Architecture and Scheduler Module for Sparse CNN Accelerators.

Jingyu Wang, Zhe Yuan, Ruoyang Liu, Xiaoyu Feng, Li Du, Huazhong Yang, Yongpan Liu

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020

14.2 A 65nm 24.7µJ/Frame 12.3mW Activation-Similarity-Aware Convolutional Neural Network Video Processor Using Hybrid Precision, Inter-Frame Data Reuse and Mixed-Bit-Width Difference-Frame Data Codec.

Zhe Yuan, Yixiong Yang, Jinshan Yue, Ruoyang Liu, Xiaoyu Feng, Zhiting Lin, Xiulong Wu, Xueqing Li, Huazhong Yang, Yongpan Liu

Proceedings of the 2020 IEEE International Solid- State Circuits Conference, 2020

2019

A 65nm 0.39-to-140.3TOPS/W 1-to-12b Unified Neural Network Processor Using Block-Circulant-Enabled Transpose-Domain Acceleration with 8.1 × Higher TOPS/mm²and 6T HBST-TRAM-Based 2D Data-Reuse Architecture.

Jinshan Yue, Ruoyang Liu, Wenyu Sun, Zhe Yuan, Zhibo Wang, Yung-Ning Tu, Yi-Ju Chen, Ao Ren, Yanzhi Wang, Meng-Fan Chang, Xueqing Li, Huazhong Yang, Yongpan Liu

Proceedings of the IEEE International Solid- State Circuits Conference, 2019

An N-way group association architecture and sparse data group association load balancing algorithm for sparse CNN accelerators.

Jingyu Wang, Zhe Yuan, Ruoyang Liu, Huazhong Yang, Yongpan Liu

Proceedings of the 24th Asia and South Pacific Design Automation Conference, 2019