Rung-Bin Lin

ACM Trans. Design Autom. Electr. Syst., 2018

Designing and Benchmarking of Double-Row Height Standard Cells.

[BibT_eX]

[DOI]

Proceedings of the 2018 IEEE Computer Society Annual Symposium on VLSI, 2018

Recognition of regular layout structures.

[BibT_eX]

[DOI]

Yu-Cheng Chiang

Shr-Cheng Tsai

Proceedings of the 19th International Symposium on Quality Electronic Design, 2018

2017

On Benchmarking Pin Access for Nanotechnology Standard Cells.

[BibT_eX]

[DOI]

Shang-Rong Fang

Cheng-Wei Tai

Proceedings of the 2017 IEEE Computer Society Annual Symposium on VLSI, 2017

Overview of the 2017 CAD contest at ICCAD: Invited paper.

[BibT_eX]

[DOI]

Proceedings of the 2017 IEEE/ACM International Conference on Computer-Aided Design, 2017

A Maze Routing-Based Algorithm for ML-OARST with Pre-Selecting and Re-Building Steiner Points.

[BibT_eX]

[DOI]

Proceedings of the on Great Lakes Symposium on VLSI 2017, 2017

2016

Design Space Exploration of FinFETs with Double Fin Heights for Standard Cell Library.

[BibT_eX]

[DOI]

Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2016

Overview of the 2016 CAD contest at ICCAD.

[BibT_eX]

[DOI]

Proceedings of the 35th International Conference on Computer-Aided Design, 2016

Practical ILP-based routing of standard cells.

[BibT_eX]

[DOI]

Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition, 2016

Multiple-patterning lithography-aware routing for standard cell layout synthesis.

[BibT_eX]

[DOI]

Kuen-Wey Lin

Yih-Lang Li

Proceedings of the 2016 IEEE Asia Pacific Conference on Circuits and Systems, 2016

2015

A router for via configurable structured ASIC with standard cells and relocatable IPs.

[BibT_eX]

[DOI]

Proceedings of the Sixteenth International Symposium on Quality Electronic Design, 2015

Overview of the 2015 CAD Contest at ICCAD.

[BibT_eX]

[DOI]

Natarajan Viswanathan

Shih-Hsu Huang

Myung-Chul Kim

Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2015

Simultaneous transistor pairing and placement for CMOS standard cells.

[BibT_eX]

[DOI]

Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015

2014

Transition inversion coding with parity check for off-chip serial transmission.

[BibT_eX]

[DOI]

Jian Zeng

Jian-Yang Zhou

Proceedings of the 21st IEEE International Conference on Electronics, Circuits and Systems, 2014

Logic block and design methodology for via-configurable structured ASIC using dual supply voltages.

[BibT_eX]

[DOI]

Proceedings of the Great Lakes Symposium on VLSI 2014, GLSVLSI '14, Houston, TX, USA - May 21, 2014

2013

Relocatable and resizable SRAM synthesis for via configurable structured ASIC.

[BibT_eX]

[DOI]

Hsin-Hung Liu

I-Lun Tseng

Proceedings of the International Symposium on Quality Electronic Design, 2013

Slack budgeting and slack to length converting for multi-bit flip-flop merging.

[BibT_eX]

[DOI]

Chia-Chieh Lu

Proceedings of the Design, Automation and Test in Europe, 2013

2012

Standard Cell Like Via-Configurable Logic Blocks for Structured ASIC in an Industrial Design Flow.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2012

$2^{n}$ Pattern Run-Length for Test Data Compression.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2012

Design and analysis of via-configurable routing fabrics for structured ASICs.

[BibT_eX]

[DOI]

Hsin-Pei Tsai

Liang-Chi Lai

Proceedings of the 2012 Design, Automation & Test in Europe Conference & Exhibition, 2012

2011

Rover: routing on via-configurable fabrics for standard-cell-like structured ASICs.

[BibT_eX]

[DOI]

Liang-Chi Lai

Hsih-Hang Chang

Proceedings of the 21st ACM Great Lakes Symposium on VLSI 2010, 2011

Clock gating optimization with delay-matching.

[BibT_eX]

[DOI]

Shih-Jung Hsu

Proceedings of the Design, Automation and Test in Europe, 2011

2010

Deterministic built-in self-test using multiple linear feedback shift registers for test power and test volume reduction.

[BibT_eX]

[DOI]

Wang-Dauh Tseng

Lung-Jen Lee

IET Comput. Digit. Tech., 2010

Clock routing for structured ASICs with via-configurable fabrics.

[BibT_eX]

[DOI]

I-Wei Lee

Wen-Hao Chen

Proceedings of the 11th International Symposium on Quality of Electronic Design (ISQED 2010), 2010

Via configurable three-input lookup-tables for structured ASICs.

[BibT_eX]

[DOI]

Proceedings of the 20th ACM Great Lakes Symposium on VLSI 2009, 2010

Power gating design for standard-cell-like structured ASICs.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation and Test in Europe, 2010

2009

Context-aware Post Routing Redundant Via Insertion.

[BibT_eX]

[DOI]

Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2009

Deterministic Built-In Self-Test Using Multiple Linear Feedback Shift Registers for Low-Power Scan Testing.

[BibT_eX]

[DOI]

Proceedings of the Eighteentgh Asian Test Symposium, 2009

A Multi-dimensional Pattern Run-Length Method for Test Data Compression.

[BibT_eX]

[DOI]

Proceedings of the Eighteentgh Asian Test Symposium, 2009

2008

Chip placement in a reticle for multiple-project wafer fabrication.

[BibT_eX]

[DOI]

Shih-Cheng Tsai

ACM Trans. Design Autom. Electr. Syst., 2008

Inter-Wire Coupling Reduction Analysis of Bus-Invert Coding.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. I Regul. Pap., 2008

Finding Dicing Plans for Multiple Project wafers fabricated with Shuttle Mask.

[BibT_eX]

[DOI]

J. Circuits Syst. Comput., 2008

Power Reduction during Scan Testing Based on Multiple Capture Technique.

[BibT_eX]

[DOI]

Lung-Jen Lee

Wang-Dauh Tseng

IEICE Trans. Electron., 2008

Variable-sized object packing and its applications to instruction cache design.

[BibT_eX]

[DOI]

Comput. Electr. Eng., 2008

Standard Cell Like Via-Configurable Logic Block for Structured ASICs.

[BibT_eX]

[DOI]

Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2008

Router and cell library co-development for improving redundant via insertion at pins.

[BibT_eX]

[DOI]

Wei-Chiu Tseng

Yu-Hsing Chen

Proceedings of the 26th International Conference on Computer Design, 2008

2007

Reticle Design for Minimizing Multiproject Wafer Production Cost.

[BibT_eX]

[DOI]

Shih-Cheng Tsai

IEEE Trans Autom. Sci. Eng., 2007

Conjugate conflict continuation graphs for multi-layer constrained via minimization.

[BibT_eX]

[DOI]

Shuyu Chen

Inf. Sci., 2007

Reticle Exposure Plans for Multi-Project Wafers.

[BibT_eX]

[DOI]

Proceedings of the 10th IEEE Workshop on Design & Diagnostics of Electronic Circuits & Systems (DDECS 2007), 2007

Double-via-driven standard cell library design.

[BibT_eX]

[DOI]

Proceedings of the 2007 Design, Automation and Test in Europe Conference and Exposition, 2007

2006

Is more redundancy better for on-chip bus encoding.

[BibT_eX]

[DOI]

Hsun-Chieh Yu

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

Design space exploration for minimizing multi-project wafer production cost.

[BibT_eX]

[DOI]

Proceedings of the 2006 Conference on Asia South Pacific Design Automation: ASP-DAC 2006, 2006

2005

A Comparative Study on Dicing of Multiple Project Wafers.

[BibT_eX]

[DOI]

Proceedings of the 2005 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2005), 2005

Reticle Floorplanning and Wafer Dicing for Multiple Project Wafers.

[BibT_eX]

[DOI]

Proceedings of the 6th International Symposium on Quality of Electronic Design (ISQED 2005), 2005

Multiple project wafers for medium-volume IC production.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

Coupling reduction analysis of bus-invert coding.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

A divide-and-conquer approach to estimating minimum/maximum leakage current.

[BibT_eX]

[DOI]

Guang-Wan Liao

Ja-Shong Feng

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

Reticle floorplanning of flexible chips for multi-project wafers.

[BibT_eX]

[DOI]

Proceedings of the 15th ACM Great Lakes Symposium on VLSI 2005, 2005

2004

Multi-layer constrained via minimization with conjugate conflict continuation graphs.

[BibT_eX]

Shuyu Chen

Proceedings of the 2004 International Symposium on Circuits and Systems, 2004

2003

A Low Power-Delay Product Page-Based Address Bus Coding Method.

[BibT_eX]

[DOI]

Guang-Wan Liao

Proceedings of the 16th International Conference on VLSI Design (VLSI Design 2003), 2003

2002

Theoretical analysis of bus-invert coding.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2002

Comments on "Filling algorithms and analyses for layout density control".

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2002

An Adaptive Interconnect-Length Driven Placer.

[BibT_eX]

[DOI]

Proceedings of the 7th Asia and South Pacific Design Automation Conference (ASP-DAC 2002), 2002

Weight-Based Bus-Invert Coding for Low-Power Applications.

[BibT_eX]

[DOI]

Proceedings of the 7th Asia and South Pacific Design Automation Conference (ASP-DAC 2002), 2002

1999

Benchmark Circuits Improve the Quality of a Standard Cell Library.

[BibT_eX]

[DOI]

Isaac Shuo-Hsiu Chou

Proceedings of the 1999 Conference on Asia South Pacific Design Automation, 1999

Low Power CMOS Off-Chip Drivers with Slew-rate Difference.

[BibT_eX]

[DOI]

Jinq-Chang Chen

Proceedings of the 1999 Conference on Asia South Pacific Design Automation, 1999

1998

A New Statistical Approach to Timing Analysis of VLSI Circuits.

[BibT_eX]

[DOI]

Proceedings of the 11th International Conference on VLSI Design (VLSI Design 1991), 1998

1994

Fuzzy logic approach to VLSI placement.

[BibT_eX]

[DOI]

Eric Q. Kang

IEEE Trans. Very Large Scale Integr. Syst., 1994

1993

An adaptive timing-driven placement for high performance VLSIs.

[BibT_eX]

[DOI]

Suphachai Sutanthavibul

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1993

1992

Fuzzy Logic Approach to Placement Problem.

[BibT_eX]

[DOI]

Proceedings of the 29th Design Automation Conference, 1992

1991

Bounds on Net Delays for Physical Design of Fast Circuits.

[BibT_eX]

Habib Youssef